C141-E034-02EN
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5.5
Ultra DMA feature set
5.5.1
Overview
Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands.
When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these
commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When
this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command
Block Register access).
Several signal lines are redefined to provide new functions during an Ultra DMA burst. These
lines assume these definitions when 1) an Ultra DMA Mode is selected, and 2) a host issues a
READ DMA or a WRITE DMA, command requiring data transfer, and 3) the host asserts
DMACK-. These signal lines revert back to the definitions used for non-Ultra DMA transfers
upon the negation of DMACK- by the host at the termination of an Ultra DMA burst. All of the
control signals are unidirectional. DMARQ and DMACK- retain their standard definitions.
With the Ultra DMA protocol, the control signal (STROBE) that latches data from DD (15:0) is
generated by the same agent (either host or device) that drives the data onto the bus. Ownership of
DD (15:0) and this data strobe signal are given either to the device during an Ultra DMA data in
burst or to the host for an Ultra DMA data out burst.
During an Ultra DMA burst a sender shall always drive data onto the bus, and after a sufficient
time to allow for propagation delay, cable settling, and setup time, the sender shall generate a
STROBE edge to latch the data. Both edges of STROBE are used for data transfers so that the
frequency of STROBE is limited to the same frequency as the data. The highest fundamental
frequency on the cable shall be 16.67 million transitions per second or 8.33 MHz (the same as the
maximum frequency for PIO Mode 4 and DMA Mode 2).
Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra
DMA Modes the device is capable of supporting. The Set transfer mode subcommand in the SET
FEATURES command shall be used by a host to select the Ultra DMA Mode at which the system
operates. The Ultra DMA Mode selected by a host shall be less than or equal to the fastest mode
of which the device is capable. Only the Ultra DMA Mode shall be selected at any given time. All
timing requirements for a selected Ultra DMA Mode shall be satisfied. Devices supporting Ultra
DMA Mode 2 shall also support Ultra DMA Modes 0 and 1. Devices supporting Ultra DMA
Mode 1 shall also support Ultra DMA Mode 0.
An Ultra DMA capable device shall retain its previously selected Ultra DMA Mode after
executing a Software reset sequence. An Ultra DMA capable device shall clear any previously
selected Ultra DMA Mode and revert to its default non-Ultra DMA Modes after executing a Power
on or hardware reset.
Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an
Ultra DMA burst the host sends the its CRC data to the device. The device compares its CRC data
to the data sent from the host. If the two values do not match the device reports an error in the
error register at the end of the command. If an error occurs during one or more Ultra DMA bursts
for any one command, at the end of the command, the device shall report the first error that
occurred.
Summary of Contents for MPA3017AT
Page 1: ...C141 E034 02EN MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT DISK DRIVES PRODUCT MANUAL ...
Page 29: ...C141 E034 02EN 3 2 Figure 3 1 Dimensions ...
Page 44: ...C141 E034 02EN 4 5 Figure 4 2 MPA30xxAT Block diagram ...
Page 50: ...C141 E034 02EN 4 11 Figure 4 4 Read write circuit block diagram ...
Page 52: ...C141 E034 02EN 4 13 Figure 4 6 PR4 signal transfer ...
