C141-E054-02EN
4 - 47
l.
Cache segment count
This parameter specifies the number of cache segments used by the IDD. This parameter
is valid when the SIZE bit specification is "0."
The INIT can specify X'01' to X'10' in this parameter. When X'00' is specified in this
parameter, the IDD performs rounding processing of the parameter. When a value greater
than x10 is specified, the IDD performs rounding processing and sets X'10'. The default
value of this parameter is "04" (=972K x 4) (MAA3182FC) and "08" (=468K x 8)
(MAF3364FC, MAG3091FC, MAG3182FC).
This parameter indicates the same value for all initiators and if it is changed by any
initiator, a UNIT ATTENTION condition (UNIT ATTENTION [=6] / Mode select
parameter changed [=2A-01]) is generated for all the initiators that did not change it.
Mode select parameter (page 8-byte 13)
Cache segment length
1
3,888 KB
2
1,944 KB
3
1,296 KB
4
(default of MAA3182FC)
972 KB
5
777 KB
6
648 KB
7
555 KB
8
(default of MAF3364FC, MAG3091FC,
MAG3182FC)
486 KB
9
432 KB
10
388 KB
11
353 KB
12
324 KB
13
299 KB
14
277 KB
15
259 KB
16
243 KB
m. LBCSS (logical block cache segment size)
This bit is not supported in this IDD.
The IDD disregards the value in this bit.
Summary of Contents for MAA3182FC Series
Page 5: ...This page is intentionally left blank ...
Page 9: ...viii C141 E054 02EN This page is intentionally left blank ...
Page 11: ...This page is intentionally left blank ...
Page 21: ...This page is intentionally left blank ...
Page 131: ...This page is intentionally left blank ...
Page 143: ...This page is intentionally left blank ...
Page 311: ...This page is intentionally left blank ...
Page 313: ...This page is intentionally left blank ...
Page 324: ...This page is intentionally left blank ...
Page 327: ......