Fujitsu F2MC-8L Series, Hardware Manual, Page: 78 / 131

HARDWARE CONFIGURATION
2-58
12-BIT MULTIPUL
GENERATOR
(MPG, TIMER 4)
[Bits 5 and 4] CKS1 and CKS0: Count clock pulse select bits
Bits 5 and 4 are used to select the count clock pulse (minimum resolution) in
the PWM or PPG operation mode.
0
0
1
1
1 system clock cycle (0.5
µ
s at 8 MHz)
2 system clock cycles (1.0
µ
s at 8 MHz)
4 system clock cycles (2.0
µ
s at 8 MHz)
8 system clock cycle (4.0
µ
s at 8 MHz)
0
1
0
1
CKS1 CKS0
Clock pulse to be selected
(at maximum gear speed)
Maximum cycle at maximum
gear speed (4096 clock pulses)
2048.0
µ
s at 8 MHz (488 Hz)
4096.0
µ
s at 8 MHz (244 Hz)
8192.0
µ
s at 8 MHz (122 Hz)
1638.42
µ
s at 8 MHz (61 Hz)
One system clock cycle is 500 ns at 8 MHz and maximum gear speed.
These bits should be set during operation stop.
[Bit 3] SPOL: Output polarity select bit
Bit 3 is used to select the polarity of the waveform output from the MPG. This
bit should be set during operation stop.
0
1
Outputs MPG output waveform with positive polarity
Reverses MPG output waveform for output
[Bit 2] STRG: Software trigger bit
When the internal trigger mode is selected, when 1 is set at this bit, the timer
and prescaler are cleared and the timer is started. This bit also provides
start by a software trigger. 0 is always read when this bit is read.
0
1
Ignored
Clears timer and prescaler to start timer
[Bits 1 and 0] PCN1 and PCN0: Port output select/overcurrent detect
function control bits
Bits 1 and 0 are used to control whether or not the MPG pulse output pin is
used as the general-purpose pin and set the effective/ineffective edge of the
DTTI input for overcurrent detection. The operation mode should be set dur-
ing operation stop.
When the DTTI input is enabled, if an error is detected outside the chip, the
MPG output can be set to an inactive level (initial output) by inputting the
edge. At this time, the timer and prescaler are cleared to the stopped state.
To restart output, 0 must be written at the overcurrent detect interrupt re-
quest bit to clear the flag. At this time, the MPG restarts outputting the wave-
forms set when the DTTI input was detected from the timer value of
00
H
after
accepting the effective trigger input.
After the DTTI is input in the effective state (PCN1 = 1), if the operation mode
is selected to clear the DTIR flag of the INSTR register, the MPG output goes
inactive in the selected mode.