Fujitsu F2MC-8L Series, Hardware Manual, Page: 70 / 131

HARDWARE CONFIGURATION
2-50
8/16-BIT TIMER
(TIMER 2 AND TIMER 3)
[Bit 1] T2STP: Timer-stop bit
Counting continued without clearing counter
Counting suspended
0
1
[Bit 0] T2STR: Timer-start bit
Terminates operation
Clears counter and starts operation
0
1
Address: 0018
H
Initial value
X000XXX0
B
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T3IF T3IE — — T3CS1 T3CS0 T3STP T3STR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(2) Timer 3 control register (T3CR)
T3CR
T2CR
T3DR
T2DR
Address: 0018
H
Address: 0019
H
Address: 001A
H
Address: 001B
H
[Bit 7] T3IF: Interrupt request flag bit
(When write)
Interrupt request flag clearing
No operation
0
1
(When read)
No interrupt request
Interval interrupt request
0
1
[Bit 6] T31E: Interrupt-enable bit
Interrupt disabled
Interrupt enabled
0
1
[Bit 5]: Reserved; write 0 when writing.
[Bit 4]: Reserved; write 0 when writing.
[Bit 3 and 2]: T3CS1, T3CS0: Clock source select bit
0
1
0
1
Time cycle at 8 MHz and
Maximum gear speed
0
0
1
1
1.0
µ
s
2.0
µ
s
4.0
µ
s
16-bit mode
T2CS1 T2CS0
2 system clock cycle
4 system clock cycle
8 system clock cycle
—
System clock cycle
Note: When bit 2 and 3 use only timer 2, set this bit to except 11.