Fujitsu F2MC-8L Series, Hardware Manual, Page: 69 / 131

HARDWARE CONFIGURATION
2-49
8/16-BIT TIMER
(TIMER 2 AND TIMER 3)
Register List
Address: 0018
H
Address: 0019
H
Address: 001A
H
Address: 001B
H
T3CR
T2CR
T3DR
T2DR
8 bit
R/W Timer-3 control register
R/W Timer-2 control register
R/W Timer-3 data register
R/W Timer-2 data register
Description of Register Details
The detail of each register is described below.
(1) Timer 2 control register (T2CR)
T3CR
T2CR
T3DR
T2DR
Address: 0018
H
Address: 0019
H
Address: 001A
H
Address: 001B
H
Address: 0019
H
Initial value
X000XXX0
B
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T2IF T2IE — — T2CS1 T2CS0 T2STP T2STR
(R/W) (R/W) — — (R/W) (R/W) (R/W) (R/W)
[Bit 7] T2IF: Interrupt request flag bit
(When write)
Interrupt request flag clearing
No operation
0
1
(When read)
No interrupt request
Interval interrupt request
0
1
[Bit 6] T2IE: Interrupt-enable bit
Interrupt disabled
Interrupt enabled
0
1
[Bit 5]: Reserved; write 0 when writing.
[Bit 4]: Reserved; write 0 when writing.
[Bit 3 and 2] T2CS1, T2CS0: Clock source select bit
0
1
0
1
Time cycle at 8 MHz and
Maximum gear speed
0
0
1
1
Rising edge of external clock pulse
Falling edge of external clock pulse
Both edges of external clock pulse
4.00
µ
s
T2CS1 T2CS0
8 system clock cycle
System clock cycle
Note: One system clock cycle is 500 ns at 8 MHz and maximum gear speed.