Fujitsu F2MC-8L Series Hardware Manual Download Page 117

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INSTRUCTIONS

4-3

4.1 TRANSFER INSTRUCTIONS

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48

MOV dir,A
MOV @IX+off,A
MOV ext,A
MOV @EP,A
MOV Ri,A

MOV A,#d8
MOV A,dir
MOV A,@IX+off
MOV A,ext
MOV A,@A

MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX+off,#d8
MOV @EP,#d8

MOV Ri,#d8
MOVW dir,A
MOVW @IX+off,A
MOVW ext,A
MOVW @EP,A

MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX+off
MOVW A,ext

MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A

MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T

MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP

SETB dir:n
CLRB dir:n
XCH A,T
XCHW A,T
XCHW A,EP

XCHW A,IX
XCHW A,SP
MOVW A,PC

3
4
4
3
3

2
3
4
4
3

3
3
4
5
4

4
4
5
5
4

2
3
4
5
5

4
4
2
3
2

2
2
2
3
4

3
2
2
3
2

4
4
2
3
3

3
3
2

2
2
3
1
1

2
2
2
3
1

1
1
3
3
2

2
2
2
3
1

1
3
2
2
3

1
1
1
3
1

1
1
1
1
1

3
1
1
3
1

2
2
1
1
1

1
1
1

(dir)

←

(A)

((IX)+off)

←

(A)

(ext)

←

(A)

((EP))

←

(A)

(Ri)

←

(A)

←

(A)

←

dir

(A)

←

((IX)+off)

(A)

←

(ext)

(A)

←

((A))

(A)

←

((EP))

(A)

←

(Ri)

(dir)

←

((IX)+off)

←

((EP))

←

(Ri)

←

(dir)

←

(AH),(dir+1)

←

(AL)

((IX)+off)

←

(AH),((IX)+off+1)

←

(AL)

(ext)

←

(AH),(ext+1)

←

(AL)

((EP))

←

(AH),((EP)+1)

←

(AL)

(EP)

←

(A)

←

d16

(AH)

←

(dir),(AL)

←

(dir+1)

(AH)

←

((IX)+off),(AL)

←

((IX)+off+1)

(AH)

←

(ext),(AL)

←

(ext+1)

(AH)

←

((A)),(AL)

←

((A)+1)

(AH)

←

((EP)),(AL)

←

((EP)+1)

(A)

←

(EP)

←

d16

(IX)

←

(A)

←

(IX)

(SP)

←

(A)

←

(SP)

((A))

←

(T)

((A))

←

(TH),((A)+1)

←

(TL)

(IX)

←

d16

(A)

←

(PS)

←

(A)

(SP)

←

d16

(AH)

⇔

(AL)

(dir):n

←

(dir):n

←

(AL)

⇔

(TL)

(A)

⇔

(T)

(A)

⇔

(EP)

(A)

⇔

(IX)

(A)

⇔

(SP)

(A)

←

(PC)

—
—
—
—
—

AL
AL
AL
AL
AL

AL
AL

—
—
—

—
—
—
—
—

—

AL
AL
AL
AL

AL
AL

—
—
—

—
—
—
—
—

—
—

AL
AL

—

—
—
—

—
—
—
—
—

—

AH
AH
AH
AH

AH
AH

—
—
—

—
—
—
—
—

—
—
—

—

—
—
—

—
—
—
—
—

—

dH
dH
dH
dH

dH
dH
dH

—
—

—

—
—

—

—
—

—
—
—

dH
dH

dH
dH
dH

— — — —
— — — —
— — — —
— — — —
— — — —

+ + — —
+ + — —
+ + — —
+ + — —
+ + — —

+ + — —
+ + — —
— — — —
— — — —
— — — —

— — — —
— — — —
— — — —
— — — —
— — — —

— — — —
+ + — —
+ + — —
+ + — —
+ + — —

+ + — —
+ + — —
— — — —
— — — —
— — — —

— — — —
— — — —
— — — —
— — — —
— — — —

— — — —
— — — —
+ + + +
— — — —
— — — —

— — — —
— — — —
— — — —
— — — —
— — — —

— — — —
— — — —
— — — —

45
46
61
47

48 to 4F

04
05
06
60
92

08 to 0F

85
86
87

88 to 8F

D5
D6
D4
D7

E3
E4

C5
C6
C4

E7
E2

82
83

70
71

A8 to AF

A0 to A7

42
43

F6
F5
F0

MNEMONIC

N Z V C

OP CODE

OPERATION

Notes

1. In byte transfer to A, T

←

A is only for low bytes.

2. Operands for two or more operand instructions should be stored in the order designated in MNEMONIC

(Opposite order to F

MC-8 family).

3 ~ indicates the number of instruction cycles and # indicates the number of instruction bytes.

Summary of Contents for F2MC-8L Series

Page 1: ...F2MC 8L FAMILY MICROCONTROLLERS MB89140 SERIES HARDWARE MANUAL FUJITSU SEMICONDUCTOR MICROCONTROLLER MANUAL CM25 10113 1E ...

Page 2: ...information contained in this document has been carefully checked and is believed to be reliable However Fujitsu assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Fujitsu Fujitsu reserves the right to change products or specifications without notice No part of this ...

Page 3: ...llation frequency 2 A system clock cycle is the clock frequency divided by the gear function see 2 2 One cycle time of the system clock varies with the settings of the CS1 and CS0 bits of the SYCC register With some internal resources the gear change will cause changes in operating speed See 3 4 for details ...

Page 4: ...R 4 2 55 2 11 8 BIT SERIAL I O 2 70 2 12 A D CONVERTER 2 76 2 13 BUZZER OUTPUT CIRCUIT 2 83 2 14 EXTERNAL INTERRUPT CIRCUIT 2 85 3 OPERATION 3 1 3 1 CLOCK PULSE GENERATOR 3 3 3 2 RESET 3 4 3 2 1 Reset Operation 3 4 3 2 2 Reset Sources 3 5 3 3 INTERRUPT 3 6 3 4 LOW POWER CONSUMPTION MODES 3 8 3 5 PIN STATES FOR SLEEP STOP AND RESET 3 9 4 INSTRUCTIONS 4 1 4 1 TRANSFER INSTRUCTIONS 4 3 4 2 OPERATION ...

Page 5: ...Operating State of Low power Consumption Modes 2 15 Table 2 3 Sources of Reset 2 20 Table 2 4 List of Port Functions 2 25 Table 2 5 Port register 2 26 Table 2 6 Relationship between value Set at OUTCR and Duty 2 65 Table 2 7 Buzzer Output Frequencies at 8 0 MHz of oscillation frequency 2 84 Table 3 1 Interrupt Sources and Interrupt Vectors 3 7 Table 3 2 Low power Consumption Mode at Each Clock Mod...

Page 6: ...ram 2 34 Fig 2 20 Watchdog Timer Reset Block Diagram 2 36 Fig 2 21 Time base Timer Block Diagram 2 41 Fig 2 22 8 bit PWM Timer Timer 1 Block Diagram 2 43 Fig 2 23 Timer Operation 2 46 Fig 2 24 PWM Pulse Output 2 47 Fig 2 25 8 16 bit Timer Block Diagram 2 48 Fig 2 26 Description Diagram for Internal Clock Mode Operation 2 52 Fig 2 27 Flow Diagram for Timer Setting 2 52 Fig 2 28 External Cock Mode O...

Page 7: ...1 GENERAL 1 1 FEATURES 1 3 1 2 PRODUCT SERIES 1 5 1 3 BLOCK DIAGRAM 1 7 1 4 PIN ASSIGNMENT 1 8 1 5 PIN FUNCTION DESCRIPTION 1 10 1 6 HANDLING DEVICES 1 16 ...

Page 8: ...t and branch instruction Bit handling instruction etc Operation at low voltage A D converter unused 25 segment VFD Vacuum Fluorescent Display driver Low current dissipation applicable to dual circuit clock Internal high withstand voltage ports 5 timers 8 bit PWM timer available as reload timer 12 bit MPG timer available as PPG output PWM output and reload timer 8 16 bit timer counter available as ...

Page 9: ...RAL 1 4 MB89144 ROM 12K RAM 256 Planned MB89147 ROM 32K RAM 1K Under development MB89145 ROM 16K RAM 512 Under development MB89146 ROM 24K RAM 768 Planned Small Large Memory capacity Fig 1 1 MB89140 series ...

Page 10: ... port N channel open drain 1 P31 Total 55 VFD 25 segment Capable of generating four internal pulses of 0 26 ms 0 51 ms 1 02 ms and 0 524 s at oscillation frequency of 8 0 MHz 8 bit timer operation toggle output possible 1 2 8 or 16 system clock cycles of operating clock 8 bit resolution PWM operation conversion cycle 128 µs to 2 0 ms at oscillation frequency of 8 0 MHz and maximum gear speed 12 bi...

Page 11: ...dependent channels edge selection interrupt vector interrupt source flag External interrupt Interrupt mode selectable from rising edge falling edge or both edge Analog noise filter built in For releasing Stop Sleep modes edge detection possible in Stop mode Standby mode Sleep Stop and Watch mode Process CMOS Package DIP 64P M01 SDIP 64 FPT 64P M06 QFP64 Operating voltage 2 7 V to 6 0 V 2 7 V to 6 ...

Page 12: ...k oscillator Max 8 MHz Clock control Sub clock oscillator 32 768 kHz Port 7 CMOS input port Port 2 CMOS output port 8 bit PWM timer Mode control 10 bit A D converter Port 0 1 CMOS output port Time base timer Buzzer High withstand voltage port 6 High withstand voltage port 5 High withstand voltage port 4 8 bit serial 12 bit MPG Port 3 8 16 bit timer counter External interrupt input CMOS I O port Ot...

Page 13: ...0 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 65 66 67 68 69 70 71 72 73 74 75 76 77 78 A15 VAA A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS 92 91 90 89 88 87 86 85 84 83 82 81 80 79 VCC A14 A13 A8 A9 A11 OE A10 CE O8 O7 O6 O5 O4 TOP VIEW Items in dotted lines are only available for the MB89PV140 The SH DIP64 cautions are as follows Pins 33 and 34 serve as input on...

Page 14: ...dotted lines are only available for the MB89PV140 20 21 22 23 24 25 26 27 28 29 30 31 32 P01 P63 P65 P67 VCC AVSS AN1 P00 P02 P62 P64 P66 BZ AVCC AN0 AN2 P23 MODA X1 P71 P22 P20 P36 WDG X1A PWO1 RST X0 VSS P70 P21 P37 X0A PWO0 DTTI 84 83 82 81 80 79 78 94 95 96 65 66 67 68 64 63 62 61 60 59 58 57 56 55 54 53 52 65 N C 73 A2 81 N C 89 OE 66 A15 VPP 74 A1 82 O4 90 N C 67 A12 75 A0 83 O5 91 A11 68 A7...

Page 15: ...nput is hysteresis type containing a noise filter This port also serves as an external start pin for the A D converter General purpose I O ports Input is hysteresis type containing a noise filter General purpose I O ports Input is hysteresis type containing a noise filter Although these ports serve as analog input pins analog input does not pass through the noise filter for hysteresis input Can be...

Page 16: ...ter This port also serves as an external interrupt pin Interrupt input is also hysteresis type containing a noise filter General purpose I O port Input is hysteresis type containing a noise filter This port can also be used as an external interrupt pin or MPG trigger input pin Interrupt input is also hysteresis type containing a noise filter Used for buzzer output only 1 58 BZ H This pin also serv...

Page 17: ...Function Pin No Pin Name Circuit type 64 57 VCC Used for power supply 32 25 VSS Used for power supply GND 63 56 AVCC Used for power supply for A D converter Used for power supply for A D converter Must be used at same potential as VSS pin SDIP 62 55 AVSS SDIP ...

Page 18: ... 77 79 03 78 80 VSS Output Power GND pin 79 82 04 80 83 05 81 84 06 Input Data input pins 82 85 07 83 86 08 84 87 CE Output Chip enable pin for ROM A High level is output in the standby mode 85 88 A10 Output Address output pin 86 89 OE Output Output enable pin for ROM A Low level is always output 87 91 A11 88 92 A9 Output Address output pins 89 93 A8 90 94 A13 Output Address output pin 91 95 A14 O...

Page 19: ...put N ch open drain output CMOS hysteresis input with noise filter CMOS output CMOS hysteresis input with noise filter analog input excluded X1 X0 Standby control signal A B C D E F Pch R Nch Pch Nch Nch Pch Nch Hysteresis input with noise filter Hysteresis input with noise filter Analog input Port Hysteresis input with noise filter Fig 1 5 Input Output Circuit Configurations ...

Page 20: ...ng MB89V140 microcontroller CMOS output CMOS hysteresis input with noise filter The pull up resistor is optional CMOS hysteresis input with noise filter G H I J Pch Nch Hysteresis input with noise filter Port Pch R Pch P channel high withstand voltage open drain output VFD Port Hysteresis input with noise filter Fig 1 5 Input Output Circuit Configurations Continued ...

Page 21: ...e at the supply frequency 50 to 60 Hz should be less than 10 of the typical VCC value or the coefficient of excessive variation should be less than 0 1 V ms instanta neous change when the power supply is switched 5 Precautions for external clocks It takes some time for oscillation to stabilize after changing the mode to power on reset option selection and stop Consequently an external clock must b...

Page 22: ... 2 5 WATCH PRESCALER 2 34 2 6 WATCHDOG TIMER RESET 2 36 2 7 TIME BASE TIMER 2 41 2 8 8 BIT PWM TIMER TIMER 1 2 43 2 9 8 16 BIT TIMER TIMER 2 AND TIMER 3 2 48 2 10 12 BIT MULTIPUL GENERATOR MPG TIMER 4 2 55 2 11 8 BIT SERIAL I O 2 70 2 12 A D CONVERTER 2 76 2 13 BUZZER OUTPUT CIRCUIT 2 83 2 14 EXTERNAL INTERRUPT CIRCUIT 2 85 ...

Page 23: ...reset vectors and vector call instructions are at the highest address Figure 2 1 shows the structure of the memory space for the MB89140 series of microcontrollers FFFFH 8007H 8000H 0480H 0200H 0100H 0080H 0000H RAM 1024 Register MB89P147 MB89W147 MB89PV140 I O FFFFH A000H 0380H 0200H 0100H 0080H 0000H MB89146 I O ROM 24 K ROM External ROM for MB89PV140 FFFFH C000H 0280H 0200H 0100H 0080H 0000H MB...

Page 24: ... re set and the table addresses to be referenced for the MB89145 series of mi crocontrollers Table 2 1 Table of Reset and Interrupt Vectors CALLV 0 CALLV 1 CALLV 2 CALLV 3 CALLV 4 CALLV 5 CALLV 6 CALLV 7 FFC0H FFC2H FFC4H FFC6H FFC8H FFCAH FFCCH FFCEH FFC1H FFC3H FFC5H FFC7H FFC9H FFCBH FFCDH FFCFH Upper data Lower data Table address Interrupt 11 Interrupt 10 Interrupt 9 Interrupt 8 Interrupt 7 In...

Page 25: ...f 16 bit Data in Memory This is the same as when 16 bits are specified by the operand during execu tion of an instruction Bits closer to the OP code are treated as the upper byte and those next to it are treated as the lower byte This is also the same when the memory address or 16 bit immediate data is specified by the oper and Example MOV A 5678H Extended address MOV A 1234H 16 bit immediate data...

Page 26: ... to execute 8 bit data processing instructions Stack pointer SP 16 bit long register indicating stack area Processor status PS 16 bit long register where register pointers and condition codes stored Index register IX 16 bit long register for index modification Extra pointer EP 16 bit long register for memory addressing P C A T IX EP SP PS 16 bits Program counter Accumulator Temporary accumulator I...

Page 27: ... interrupt is enabled when this flag is 1 and is disabled when it is 0 The I flag is 0 at reset IL1 and IL0 These bits indicate the level of the currently enabled inter rupt The CPU executes interrupt processing only when an interrupt with a value smaller than the value indicated by this bit is requested IL1 IL0 Interrupt level High and low 0 0 1 1 0 1 0 1 2 3 High Low No interrupt 1 N flag The N ...

Page 28: ...general purpose registers are in the register banks in memory One bank has eight registers and up to 32 banks are available for the MB89140 series of microcontrollers respectively The register bank pointer RP indicates the currently used bank Address 0100H 8 RP 32 banks Memory area R0 R1 R2 R3 R4 R5 R6 R7 Fig 2 6 Register Bank Configuration ...

Page 29: ... FFFFH RAM Internal ROM RAM Internal ROM Fig 2 7 Memory Map in Various Modes The mode that the device enters depends on the states of the device mode pins and the contents of the mode data fetched during the reset sequence The relationship between the states and operations of the device mode pins is shown below Reset vectors are read from the internal ROM Write mode for products containing EPROM M...

Page 30: ... device mode pins and the mode data fetched during the reset sequence Setting procedure Mode selected Mode pin Mode data Single chip mode 1 2 0 XXXXX000 Power on Device mode pin Reset cancel Fetch programs from internal ROM User ROM 1 Set 0 at the MODA pin 2 All pin ports fetch internal mode data and reset vec tors No Yes ...

Page 31: ... Stop Clock specification CPU operation clock Resource operation clock Clock for time base timer Clock for watch prescaler Selector HC1 HC2 HC3 HC4 LC from watch Stop release signal Subclock pulse generator From time base timer Ready signal Hold request signal Hold acknowledge signal Fig 2 8 Machine Clock Control Block Diagram Register List Main sub clock control block consists of standby control ...

Page 32: ...itching the CPU and resources to the sleep mode 0 1 No operation Sleep mode This bit is cleared at reset sleep or stop cancellation 0 is always read when this bit is read Bit 5 SPL Pin state specifying bit This bit is used to specify the external pin state in the stop mode 0 1 Holds state and level immediately before stop mode High impedance This bit is cleared at resetting Bit 4 RST Software rese...

Page 33: ...4 and Bit 3 WT1 and WT0 Oscillation stabilization time select bits These bit are used to select the oscillation stabilization wait time of the main clock 1 1 0 0 Approximate 218 fCH Approximate 217 fCH Approximate 214 fCH Approximate 24 fCH 1 0 1 0 WT1 WT0 Oscillation stabilization time Oscillation stabilization time with 8 MHz source clock 32 8 ms 16 4 ms 2 0 ms 0 ms fCH Oscillation frequency of ...

Page 34: ...ts main clock 8 MHz mode 0 1 Bits 1 and 0 CS1 and CS0 System clock select bits Gear function If the main mode is specified by the system clock select bit SCS the sys tem clock is as given in the table below 0 0 1 1 64 fCH 16 fCH 8 fCH 4 fCH 0 1 0 1 CS1 CS0 Instruction cycle Instruction execution time at 8 MHz source clock 8 0 µs 2 0 µs 1 0 µs 0 5 µs fCH frequency of main clock ...

Page 35: ... 32 768 kHz Stops STOP Stops Stops Stops External interrupt RUN 250 kHz Oscillates 4 MHz 250 kHz 0 0 SLEEP Oscillates 32 768 kHz Stops STOP Stops Stops Stops External interrupt RUN 32 768 kHz Oscillates 32 768 kHz 32 768 kHz Submode SLEEP Stops Stops Stops STOP Stops Stops Stops External interrupt Watch Stops Oscillates Stops Stops Stops 32 768 kHz Watch external mode interrupt Clock mode of CPU C...

Page 36: ...level 11 is requested from a resource during the WATCH mode the WATCH mode is canceled When the I flag and IL bit are enabled like an ordinary interrupt after canceling the CPU executes the interrupt processing When they are disabled the CPU executes the interrupt processing from the instruc tion next to the one before entering the WATCH mode If the WATCH mode is canceled by inputting the reset si...

Page 37: ...hip functions stop The input output pins and output pins during the STOP mode can be controlled by the SPL bit bit 5 of the STBC register so that they are held in the mode immediately before entering the STOP mode or so that they enter in the high impedance state If an interrupt is requested when 1 is written at the STP bit bit 7 instruction execution continues without switching to the STOP mode I...

Page 38: ...WT0 bits However when Power on Reset is not specified by the mask option the CPU is not switched to the oscillation stabilization wait state even if the STOP mode is canceled by inputting the reset signal 2 Setting low power consumption mode 0 0 0 Normal 0 0 1 WATCH 0 1 0 SLEEP 1 0 0 STOP 1 Disable STP Bit 7 STBC Register SLP Bit 6 TMD Bit 3 Mode Note When the mode is switched from the subclock mo...

Page 39: ... 8 External reset or interrupt when power on reset option se lected 9 External reset or interrupt 10 External reset when power on reset option not selected 11 External reset or other reset when power on reset option selected 12 Set SCS bit to 1 13 After oscillation stabilized 14 Set STP bit to 1 15 Set TMD bit to 1 16 Set SLP bit to 1 17 External reset after oscillation stabilized or when power on...

Page 40: ...ion When the power on reset and reset during the stop state are used the os cillation stabilization time is needed after the oscillator operates The time base timer or watch prescaler controls this stabilization time Consequently the operation does not start immediately even after canceling the reset However if Power on Reset Disabled is selected by the mask option no os cillation stabilization ti...

Page 41: ...X1A and P70 X0A function as input ports State transition diagram 5 8 6 7 4 1 2 3 Main RUN Main oscillate Main STOP Main stop Power on Main SLEEP Main oscillate Oscillation stabilization waiting of main clock 1 When power on reset option selected 2 When power on reset option not selected 3 After oscillation stabilized 4 Set STP bit to 1 5 Set SLP bit to 1 6 External reset when power on reset option...

Page 42: ... of same level interrupts Block Diagram Level Resource 1 Resource 2 CPU F2MC 8L bus Test register Address decorder G L Level deciding block G G G L L G G Same level priority order deciding block Interrupt vector generation block 2 Resource n Level Level Fig 2 9 Interrupt Controller Block Diagram Register List Interrupt controller consists of interrupt level registers ILR1 2 and 3 Address 007CH Add...

Page 43: ...ts the interrupt level of each resource The digits in the center of each bit correspond to the interrupt numbers IR0 IR1 IR2 IR3 IRB 0 1 2 3 11 Interrupt control module MB89140 hardware manual Interrupt number Table address Upper Lower FFFA FFF8 FFF6 FFF4 FFE4 FFFB FFF9 FFF7 FFF5 FFE5 Interrupt requests from resources L3X Example When an interrupt is requested from a resource the interrupt control...

Page 44: ...rrupt level for the applicable interrupt to the CPU d The CPU compares the interrupt level requested from the interrupt con troller with the IL bit in the processor status register e As a result of the comparison if the priority of the interrupt level is higher than that of the current interrupt processing level the contents of the I flag in the same processor status register are checked f As a re...

Page 45: ... P10 to P17 1 Resource ADST ANB ANA AN9 AN8 Parallel ports 20 to 23 P23 P22 P21 P20 P20 to P23 Resource WDG PWO0 Parallel ports 30 to 37 P37 P36 P35 P34 P33 P32 P31 P30 P30 to P37 Resource DTTI PWO1 EC SI SO SCK INT1 P40 to P47 Parallel ports 40 to 47 P47 P46 P45 P44 P43 P42 P41 P40 P50 to P57 Parallel ports 50 to 57 P57 P56 P55 P54 P53 P52 P51 P50 P60 to P67 Parallel ports 60 to 67 P67 P66 P65 P6...

Page 46: ...ta direction register DDR3 W 000DH 00000000B Ports 40 to 47 data register PDR4 R W 0010H 00000000B Ports 50 to 57 data register PDR5 R W 0011H 00000000B Ports 60 to 67 data register PDR6 R W 0012H 00000000B Ports 70 to 77 data register PDR7 R 0013H XXB Register name read write Address Initial val ue Port control register PCR0 PCR1 Address 0022H Address 0023H PCR0 PCR1 8 bit W Port control register...

Page 47: ...ut latch However when the Read Modify Write instruction is executed the contents of the output latch are read irrespec tive of the DDR setting conditions Therefore the bit processing instruc tion can be used even if input and output are mixed with each other When data is written to the PDR the written data is held in the output latch irre spective of the DDR setting conditions Operation for input ...

Page 48: ...tput can be set independently for each bit The pin with the DDR set to 1 is set to output and the pin with the DDR set to 0 is set to input Operation for output port DDR 1 The value written at the PDR is output to the pin when the DDR is set to 1 When the PDR is read usually the value of the pin is read instead of the contents of the output latch However when the Read Modify Write instruction is e...

Page 49: ...read when the PDR is read the bit processing instruction can be used even if the output level varies with load Resource output operation P23 and P21 When using as the resource output setting is performed by the resource output enable bit See the description of each resource State when reset At reset all pins are set to High impedance When a vector is fetched the output from each port is enabled an...

Page 50: ...y the value of the pin is read instead of the contents of the output latch However when the Read Modify Write instruction is executed the contents of the output latch are read irrespec tive of the DDR setting conditions Therefore the bit processing instruc tion can be used even if input and output are mixed with each other When data is written to the PDR the written data is held in the output latc...

Page 51: ...option Except for P30 Output buffer Resource output Resource output enable Resource input Fig 2 15 Ports 35 to 32 30 and 17 6 P31 N ch open drain type ports also used as resource input Switching input and output This port has a data direction register DDR and a port data register PDR for each bit Input and output can be set independently for each bit The pin with the DDR set to 1 is set to output ...

Page 52: ...setting the DDR to output State in stop modes With the SPL bit of the standby control register set to 1 in the stop mode the output impedance goes High irrespective of the value of the DDR Internal data bus PDR read Stop mode SPL 1 Input buffer Output latch DDR PDR PDR read when Read Modify Write instruction executed DDR write PDR write Pin Resource input Fig 2 16 Port 31 8 P40 to P47 P ch open dr...

Page 53: ...tor Option Fig 2 17 Ports 40 to 47 50 to 57 and 60 to 67 9 BZ P ch open drain high withstand voltage output Buzzer output A waveform at the frequency set by the buzzer register BUZR is output to the pin State when reset When reset the buzzer register BUZR is initialized to 0 and the output impedance goes High State in Stop mode With the SPL bit of the standby control register is set to 1 the outpu...

Page 54: ... 8 9 10 11 12 13 14 Subclock L0 MPX Interrupt request IRQB WIF WIE WS1 WS0 WCLR WPCR 2 31 25 ms 0 25 s 0 5 s 1 0 s Fig 2 19 Watch Prescaler Block Diagram Register list Address 000BH WPCR 8 bit R W Watch prescaler control register Description of Registers The detail of watch prescaler is described below Watch prescaler control register WPCR Address 000BH Address 0017H Initial value 00 000B Bit 7 Bi...

Page 55: ... is output This bit is cleared upon reset Bit 6 WIE Watch interrupt enable bit This bit is used to enable an interrupt by the watch Interrupt by watch disabled Interrupt by watch enabled 0 1 Bit 1 and 0 WS1 WS0 Interrupt interval time specification bit by watch These bits are used to specify the interrupt cycles 31 25 ms 0 25 s 0 50 s 1 00 s 0 0 1 1 0 1 0 1 210 fCL 213 fCL 214 fCL 215 fCL WS1 WS0 ...

Page 56: ...E0 CS Selector 2 bit counter RST Reset control Time base timer Watch prescaler CLR Start OF WDOS WDGF WDG Watchdog output control Fig 2 20 Watchdog Timer Reset Block Diagram Registers The watchdog timer reset has watchdog timer control register WDTE Address 0009H WDTE 8 bit R W Watchdog timer control register Description of Register The detail of the watchdog timer control register WDTE is describ...

Page 57: ... in this case Output from RST pin P23 as general purpose output pin reset occurs Output from P23 WDG pin reset does not occur 0 1 Note This bit is not cleared by the reset conditions This register is cleared only by a power on reset Bit 5 WDGF Watchdog output set bit Bit 5 is set to 1 when a time out of the watchdog timer is detected In this case the WDG signal is output when the WDOE is 1 Clearin...

Page 58: ...program malfunction 1 Starting watchdog timer The watchdog timer starts when 0101 is written at the watchdog timer con trol bits 2 Clearing watchdog timer When 0101 is written at the watchdog timer control bits after start the watch dog timer is cleared The counter of the watchdog timer is cleared when changing to the standby mode STOP SLEEP WATCH 3 Watchdog timer reset If the watchdog timer is no...

Page 59: ...gnal operation WDOS bit 1 with power on reset available option selected Watchdog time out WDGF bit clear P23 WDG Notes 1 The WDOS and WDGF bits are cleared only by a power on reset There fore if the power on reset unavailable option is selected this WDG out put cannot be used 2 With the power on reset available option selected and the WDGF bit set to 1 reset does not occur even if the watchdog tim...

Page 60: ... WTE3 to WTE0 to a value other than 0101 Do not set the CS bit Set the CS bit concurrently with starting the watchdog timer Write 0101 at WTE3 to WTE0 Watchdog time out Clear the WDGF flag Set WTE3 to WTE0 to a value other than 0101 Do not rewrite the CS bit Do not perform this operation at a time out NO YES ...

Page 61: ...timer does not change even with a gear change 1 2 oscillation frequency Block Diagram TBC0 TBC1 TBR TBIE TBIF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 1 2 21 bit counter TBTC Submode control signal MPX Interrupt request IRQA TBTC is a clock pulse with 1 2 oscillation of the original oscillation Fig 2 21 Time base Timer Block Diagram Register list The time base timer has time base t...

Page 62: ... occurred Interval timer overflow occurred 0 1 1 is read when the Read Modify Write instruction is read If the TBIF bit is set to 1 when the TBIE bit is 1 an interrupt request is output This bit is cleared upon reset Bit 6 TBIE Interval timer interrupt enable bit This bit is used to enable an interrupt by the interval timer Interval interrupt disabled Interval interrupt enabled 0 1 Bit 2 and 1 TBC...

Page 63: ...AR OVER FLOW Internal data bus 1 1 1 2 1 8 1 16 PWM generator and output control 8 bit counter 8 P TX P1 P0 TPE TIR OE TIE Comparator Selector 8 System clock IRQ2 Timer PWM Output Output enable signal P21 PWO0 CMR CNTR Fig 2 22 8 bit PWM Timer Timer 1 Block Diagram Register list 8 bit PWM timer consists of control registers CNTR and compare registers COMR Address 0016H Address 0017H COMR CNTR 8 bi...

Page 64: ...equest flag is cleared TIR 0 Bits 5 and 4 P1 P0 Clock select bit The following four system clock cycles can be selected by P1 and P0 0 0 1 system clock cycle 0 5 µs 0 1 2 system clock cycles 1 0 µs 1 0 8 system clock cycles 4 0 µs 1 1 16 system clock cycles 8 0 µs System clock cycle of PWM timer At 8 MHz and Maximum gear speed P1 P0 One system clock is 500 ns at 8 0 MHz and maximum gear speed Thes...

Page 65: ... is 1 the port functions as the timer PWM output pin even after the DDR of P21 is set to input bit 2 of DDR2 Bit 0 TIE Interrupt enable bit timer mode When this bit is set to 1 an interrupt occurs when the values of the counter and compare register agree Counter interrupt generation disabled Counter interrupt generation enabled 0 1 In the PWM operation mode an interrupt does not occur irrespective...

Page 66: ...is set to 1 an interrupt occurs when the values of the counter and COMR agree During interrupt processing the TIR bit is used as the interrupt flag The TIR bit is set irrespective of the value of the TIE bit However if the values of the counter and the COMR agree the TIR bit is set to 1 even after an interrupt is disabled Writing 0 at the TIR bit permits clearing of the interrupt source or the TIR...

Page 67: ...80H FFH 00H Counter value Fig 2 24 PWM Pulse Output The TIR bit of the CNTR in the PWM operation mode has no meaning No interrupt occurs irrespective of TIE bit The cycle and frequency of the PWM pulse can be changed by switching the count clock pulse The count clock pulse can be selected from four clock pulses from the prescaler PWM timer channel 1 output by the clock pulse select pits P0 and P1 ...

Page 68: ...Operable in 8 bit 2 ch mode or 16 bit 1 ch mode Block Diagram T2STR T2STP T2CS0 T2CS1 T2IE T2IF Interrupt request IRQ3 Internal data bus MPX 8 bit counter CK CLR CD Comparator EQ Compare data latch LOAD Data register Data register Compare data latch LOAD Comparator EQ T3STR T3STP T3CS0 T3CS1 T3IE T3IF 8 bit counter CLR CK Rising edge Falling edge Both edges 4 0 µs MPX 0 8 µs 1 6 µs 3 2 µs 2 2 Inte...

Page 69: ...Bit 2 Bit 1 Bit 0 T2IF T2IE T2CS1 T2CS0 T2STP T2STR R W R W R W R W R W R W Bit 7 T2IF Interrupt request flag bit When write Interrupt request flag clearing No operation 0 1 When read No interrupt request Interval interrupt request 0 1 Bit 6 T2IE Interrupt enable bit Interrupt disabled Interrupt enabled 0 1 Bit 5 Reserved write 0 when writing Bit 4 Reserved write 0 when writing Bit 3 and 2 T2CS1 T...

Page 70: ...ess 0018H Address 0019H Address 001AH Address 001BH Bit 7 T3IF Interrupt request flag bit When write Interrupt request flag clearing No operation 0 1 When read No interrupt request Interval interrupt request 0 1 Bit 6 T31E Interrupt enable bit Interrupt disabled Interrupt enabled 0 1 Bit 5 Reserved write 0 when writing Bit 4 Reserved write 0 when writing Bit 3 and 2 T3CS1 T3CS0 Clock source select...

Page 71: ...bit Operation stopped Operation started after clearing counter 0 1 Address 001BH Address 001AH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W R W R W R W R W R W R W R W Initial value XXXXXXXXB 3 Timer 1 and 2 data registers T2DR and T2DR T3CR T2CR T3DR T2DR Address 0018H Address 0019H Address 001AH Address 001BH Write data is the set interval times and read data is the counted value ...

Page 72: ...f the counter agree with the set value of the timer data registers the interval interrupt request flags T2IF and T3IF are set to 1 At this time the counter is cleared to 00H the values of the timer data registers are reloaded into the compare latch and counting is continued If the inter rupt enable bits T2IE and T3IE are set to 1 an interrupt request is output to the CPU Assuming the set value of ...

Page 73: ... request is output to the CPU FEH FFH 00H External clock Count value T2IF TSTR 1 Counter clear 01H 00H 01H 02H 00 Undefined FFH T2DR FFH T2IF 0 W Fig 2 28 External Cock Mode Operation Description Diagram 4 Precautions for use of timer stop bit If the timer stop bit is used to stop the timer the input clock pulse is fixed to HIGH Therefore the count value varies depending on the level of the input ...

Page 74: ...ays read the value twice to check that it is valid and then use the data See the 8 bit operation diagram for 16 bit mode operation 4 Starting and temporarily stopping timer The operation of the timer is described below using timer 2 a When counting after clearing the counter When the T2STR bit is 0 write 0 at the T2STP bit and 1 at the T2STR bit When the T2STR bit is set from 0 to 1 the counter is...

Page 75: ...elected The PWM operation or PPG operation at start by an external or internal trigger can be selected on a programmable basis This generator can also be used as a toggle output timer Register list Address 0024H Address 0025H Address 0026H Address 0027H Address 0028H Address 0029H MCNT INTSTR 8 bit R W Control register R W Interrupt status register CMCLBR H CMCLR H OUTCBR H OUTCR H CMCLBR L CMCLR ...

Page 76: ...register External trigger TRG input Rising edge Falling edge Both edges Interrupt status register Output compare buffer register Output compare register OUTCR 12 bit counter 4 bit prescaler Compare clear register DTTI input Rising edge Falling edge F2MC 8L internal data bus P36 PWO1 OUTCBR Comparator Comparator CMCLR 12 12 CMCLBR MPX 12 12 2 IRQ5 IRQ6 IRQ7 Q R S RST CKS RST Fig 2 30 MPG Block Diag...

Page 77: ...R W R W R W R W R W R W MCNT INTSTR CMCLBR H CMCLBR L CMCLR H CMCLR L OUTCBR H OUTCBR L OUTCR H OUTCR L Address 0026H Address 0027H Address 0028H Address 0029H Address 0024H Address 0025H Stop PWM operation mode retrigger enable 0 0 1 1 0 1 0 1 TSL1 TSL0 Operation mode PPG operation mode Retrigger disable Retrigger enable Retrigger enable mode When the start trigger software trigger or exter nal t...

Page 78: ...cted when 1 is set at this bit the timer and prescaler are cleared and the timer is started This bit also provides start by a software trigger 0 is always read when this bit is read 0 1 Ignored Clears timer and prescaler to start timer Bits 1 and 0 PCN1 and PCN0 Port output select overcurrent detect function control bits Bits 1 and 0 are used to control whether or not the MPG pulse output pin is u...

Page 79: ...trigger input interrupt compare match interrupt and compare clear interrupt It also selects the polarity of the ex ternal trigger edge Bits 7 and 6 ESL1 and ESL0 External trigger select bits Bits 7 and 6 are used to select the effective edge input of the external trig ger Input of the effective edge clears the timer and prescaler and starts the timer Address 0025H Initial value 00000000B Bit 7 Bit...

Page 80: ...re match interrupt request enabled Bit 2 CMIR Output compare match interrupt request flag Bit 2 is set to 1 when the compare match occurs Writing 0 clears this bit Writing 1 has no meaning 1 is always read when the Read Modify Write instruction is read 0 1 Output compare match interrupt not requested Output compare match interrupt requested Bit 1 DTIE Overcurrent detection interrupt enable bit Bit...

Page 81: ...mer is detected to clear the timer and set the MPG out put 4 Compare clear buffer register CMCLBR This register is used to store the compare value of compare clear The value written to the compare clear buffer register when the timer stops is written directly to the compare clear register Data transfer from the compare clear buffer register to the compare clear register after the timer starts is d...

Page 82: ...ree The pulse width can be specified by the value of this register 6 Output compare buffer register OUTCBR This register is used to store the output compare value The value written to the output compare buffer register when the timer stops is written directly to the output compare register Data transfer from the output compare buffer register to the output compare register after the timer is start...

Page 83: ...by the value of the compare clear register and the duty of the output pulse is set by the value of the output compare register Software or external trigger input Timer value Compare clear buffer register CMCLBR Compare clear register CMCLR Output compare buffer register OUTCBR Output compare register OUTCR MPG output PW00 pin output SPOL 1 03FFH 02FFH 01FFH 00FFH 01FE H 01FE H 00FF H 00FF H 03FE H...

Page 84: ...MPG output Counter and prescaler started Timer count up Yes No 12 BIT MULTIPUL GENERATOR MPG TIMER 4 Yes No Yes No When the operation mode is set to Stop or when the DTTI input is per formed with overcurrent detection enabled the MPG output pin state goes inactive in this mode Fig 2 34 Flowchart of PWM Operation Setting the TSL1 and TSL0 bit of the CNTR to 0 and 1 gives the PWM opera tion mode The...

Page 85: ...alue of the buffer can be rewritten before one cycle to change the cycle and duty The polarity of the output pulse can be changed by setting the SPOL bit For the PWM operation flow see Figure 2 34 In the initial state the timer and prescaler are stopped The MPG output is in the reset state Since the CMCLR and CMCLBR and the OUTCBR and OUTCR are connected to each other simultaneous writing is possi...

Page 86: ...PWM output The time required for this operation is 6 to 8 clock cycles Since the DTTI input is edge input the rising or falling edge can be selected To restart the PWM output after recovery from an error the DTIR flag must be cleared to provide the effective trigger input In the event of an interrupt at DTTI input other interrupt sources may be set Therefore to restart all MPG interrupt sources sh...

Page 87: ...put is reset after input of the effective trigger and the time set by the output compare register has elapsed and is set after the time set by the compare clear register has elapsed Trigger input Timer value Compare clear buffer register CMCLBR Compare clear register CMCLR Output compare buffer register OUTCBR Output compare register OUTCR MPG output PW00 pin output SPOL 1 03FFH 02FFH 01FFH 00FFH ...

Page 88: ...BIT MULTIPUL GENERATOR MPG TIMER 4 Yes No Yes No When the operation mode is set to Stop or when the DTTI input is per formed with overcurrent detection enabled the MPG output pin state goes inactive in this mode Fig 2 37 Flowchart of PPG Operation Setting the TSL1 and TSL0 bit of the CNTR to 0 and 1 or 1 and 1 gives the PPG operation mode The PPG operation mode has two modes retrigger disable and ...

Page 89: ...e must not be changed during pulse output The operation flow for PPG output is shown in Figure 2 37 The DTTI input pin is provided to inactivate the PPG output inactive at hard ware in the event of an external error When the DTTI input is set to effective when an error is detected the DTIR flag is set to inactivate the PPG output The time required for this operation is 6 to 8 clock cycles one syst...

Page 90: ...l data register SDR SI input synchronous circuit SO output synchronous circuit Output enable Output enable Internal clock pulse Shift clock counter Control circuit Shift clock pulse select Transfer direction select Serial mode register SMR Overflow D0 to D7 MSB first D7 to D0 LSB first P34 SI P33 SO P32 SCK D7 to D0 IRQ8 Clear Fig 2 38 8 bit Serial I O Block Diagram Register list The 8 bit serial ...

Page 91: ...is always read when the Read Modify Write instruction is read If this bit is set when an interrupt is enabled SIOE 1 an interrupt request is output to the CPU The meaning of each bit when writing is as follows This bit is cleared This bit does not change nor affect other bits 0 1 The end of transfer decision may be made by either the SST bit bit 0 of the SMR or by this bit Bit 6 SIOE Serial I O in...

Page 92: ...ed Bit 1 BDS Transfer direction select bit At serial data transfer this bit is used to select whether data transfer is per formed from the least significant bit first LSB first or from the most signifi cant bit first MSB first LSB first MSB first 0 1 Note that when this bit is rewritten after writing data to the SDR the data be come invalid Bit 0 SST Serial I O transfer start bit This bit is used ...

Page 93: ... SO Shift clock pulse SI P S conversion S P conversion Serial output Serial input 2 Operation modes The serial I O has three internal shift clock modes and one external shift clock mode according to the type of shift clock which are specified by the SMR Mode switching or clock selection should be made with serial I O stopped SST bit bit 0 of SMR 0 Internal shift clock mode Operation is performed b...

Page 94: ...ritten at the SST bit of the SMR and stops when 0 is written When data transfer is terminated the SST bit is automati cally cleared to 0 which stops the operation Internal shift clock mode LSB first When transfer terminated 0 1 2 5 6 7 SCK 3 4 SO SIOF SST When transfer suspended 0 1 2 5 SCK 3 4 SO SIOF SST External shift clock mode LSB first When transfer terminated 0 1 2 5 6 7 SCK 3 4 SO SIOF SST...

Page 95: ...pulse and is input from the serial input pin SI to the SDR at the rising edge of the shift clock pulse LSB first BDS 0 0 1 2 5 6 7 SCK 3 4 SO SI 0 1 2 5 6 7 3 4 SI input SO output MSB first BDS 1 7 6 5 2 1 0 SCK 4 3 SO SI SI input SO output 7 6 5 2 1 0 4 3 DI7 to DI0 indicate input data and DO7 to DO0 indicate output data Fig 2 40 Input Output Shift Timing ...

Page 96: ...Diagram Internal data bus Selector P13 ANB P12 ANA P11 AN9 P10 AN8 P07 AN7 P06 AN6 P05 AN5 P04 AN4 P03 AN3 P02 AN2 P01 AN1 P00 AN0 P17 ADST Channel selector Control Logic ADDH and ADDL ADC1 and ADC2 IRQB Comparator D A converter AVCC AVSS Sample and hold circuit Fig 2 41 A D Converter Block Diagram Register list A D converter consists of A D control status registers 1 and 2 and ADC data register A...

Page 97: ...0 0 0 0 0 0 0 0 1 1 1 1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ANS3 ANS2 Channel selected 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ANS1 ANS0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 AN8 AN9 ANA ANB ANS3 ANS2 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ANS1 ANS0 Channel selected Bit 3 ADI Interrupt flag bit The meaning of each bit to be read in the A D mode is as follows Conversion not terminated Conversion terminated 0 1 The meaning ...

Page 98: ...meaning 0 is always read The meaning of each bit to be written is as follows No change A D conversion start When EXT bit bit 1 of ADC2 is 0 0 1 2 A D converter control register 2 ADC2 The ADC2 is used to control the A D converter and to indicate its operation status ADC1 ADC2 ADDH ADDL Address 001EH Address 001FH Address 0020H Address 0021H Address 001FH Initial value 00000001B Bit 7 Bit 6 Bit 5 B...

Page 99: ...n start type Starts A D conversion with AD bit bit 0 of ADC1 0 Starts A D conversion at rising edge of clock selected by ADCK bit bit 4 of ADC2 1 Bit 0 TEST Test bit This bit is used only for testing Always write 1 at this bit 1 is always read 3 A D data registers H and L ADDH and ADDL These registers are used to store the results of A D conversion in A D mode and write the comparison set value in...

Page 100: ... bit bit 0 of the ADC1 during conversion the conversion being executed is aborted to restart the next conversion Start restart by external clock pulse Writing 1 at the EXT bit bit 1 of the ADC2 in the A D mode gives the stand by state for starting by an external clock pulse When the rising edge of the clock pulse selected by the ADCK bit bit 4 of the ADC2 is detected the conversion is started When...

Page 101: ...the rising edge of the clock pulse selected by the ADCK bit bit 4 of the ADC2 is detected the comparison is started When a clock pulse is provided at the rising edge during comparison the comparison being executed is aborted to restart the comparison If the comparison or recomparison is executed by the external clock pulse with the EXT bit bit 1 of the ADC2 set to 1 it cannot be compared or recom ...

Page 102: ...EXT bit bit 1 of the ADC2 to 0 when the operation is stopped ADMV bit bit 2 of the ADC1 is 0 and then inhibit starting by the external clock pulse If the start is made by software AD bit bit 1 of the ADC1 the analog input channel for restart can be switched and the interrupt source in the Sense mode can be changed 4 To switch between the A D and Sense modes clear the interrupt flag bit ADI bit bit...

Page 103: ... can be output by setting the registers Block Diagram Internal bus TBR BUZ1 BUZ0 TBCR BUZR 1 210 1 211 10 11 Select CLR CK 1 2 frequency 10 0 MHz Time base timer Selector BZ P ch high withstand voltage port Fig 2 42 Buzzer Output Circuit Block Diagram Registers The buzzer output block has buzzer register BUZR Address 000EH BUZR 8 bit R W Buzzer register ...

Page 104: ... in the table below are selected Table 2 7 Buzzer Output Frequencies at 8 0 MHz of oscillation frequency High impedance Set H 3 91 kHz 1 95 kHz Buzzer output frequency 0 0 1 1 BUZ1 0 1 0 1 BUZ0 Description of Operation This circuit outputs a signal for use as a check sound The buzzer register is used to enable buzzer output and select the frequency Setting 00 at the BUZR register produces a square...

Page 105: ...agram EIR1 SL11 SL10 EIE1 EIR0 SL01 SL00 EIE0 1 0 0 1 0 0 MPX MPX INT1 INT0 X 0 1 X 0 1 IRQ1 IRQ0 EIC Fig 2 43 External Interrupt Circuit Block Diagram Register List Address 000FH EIC 8 bit R W External interrupt control register Description of Registers External interrupt control register EIC The EIC controls an interrupt by the IRQ pin EIC Address 000FH Address 000FH Initial value 00000000B Bit ...

Page 106: ...t 5 SL11 SL10 Edge polarity mode select bit These bits are used to control the input edge polarity of the INT1 pin Both edge mode Rising edge Falling edge 1 0 0 1 0 SL11 SL10 Selection of external interrupt enable edge Bit 4 EIE1 Interrupt enable bit This bit is used to enable an external interrupt request by the INT1 pin Interrupt request disabled Interrupt request enabled by EIR1 setting 0 1 Bit...

Page 107: ...ge mode Rising edge Falling edge 1 0 0 1 0 SL11 SL10 Selection of external interrupt enable edge Bit 0 EIE0 Interrupt enable bit Bit 0 is used to enable an external interrupt request by the INT0 pin Interrupt request disabled Interrupt request enabled by EIR0 setting 0 1 Precautions for Using External Interrupt Circuit To enable the interrupt after reset is cleared clear the interrupt flag at the ...

Page 108: ...3 1 CLOCK PULSE GENERATOR 3 3 3 2 RESET 3 4 3 3 INTERRUPT 3 6 3 4 LOW POWER CONSUMPTION MODES 3 8 3 5 PIN STATES FOR SLEEP STOP AND RESET 3 9 3 OPERATION ...

Page 109: ...ulses can also be supplied internally by inputting externally generated clock pulses to the X0 pin The X1 pin should be kept open The X0A and X1A pins are used for the subclock and function in the same manner as the X0 and X1 pins When the single channel clock option is selected the X0A and X1A pins serve as the P70 and P71 pins re spectively Xtal C C MB8914X X0 X1 OSC MB8914X X0 X1 OPEN Xtal C C ...

Page 110: ...ta from address FFFDH the upper bytes of the reset vec tors from address FFFEH and the lower bytes from address FFFFH in that order Figure 3 2 shows the flow chart for the reset operation Reset clear Execute the next instruction Fetch reset vectors from addresses FFFEH and FFFFH Fetch instruction codes from reset vectors and execute the instruction Fetch mode data from address FFFDH Fig 3 2 Outlin...

Page 111: ...The watchdog function is enabled by the watchdog control register and reaccess to this register is not obtained within the specified time When the stop mode is cleared by reset or power on reset operation is started after elapse of the oscillation stabilization time For details see pages 2 19 and 2 20 Note In modes other than Stop the external reset input is sampled by the external clock pulse The...

Page 112: ...g registers ILR1 to ILR3 in the interrupt controller The interrupt level can be set from 1 to 3 where 1 indicates the highest level and 2 the second highest level Level 3 indicates that no interrupt occurs The interrupt request of this level cannot be accepted After initializing the registers the main program executes various controls 2 Interrupts are generated from the resources 3 The highest pri...

Page 113: ...al interrupt 0 IRQ1 External interrupt 1 IRQ2 8 bit PWM timer Timer 1 IRQ3 8 16 bit timer counter Timer 2 IRQ4 8 16 bit timer counter Timer 3 IRQ5 12 bit MPG CMIR IRQ6 12 bit MPG CLIR IRQ7 12 bit MPG DTIR IRQ8 8 bit serial I O IRQ9 A D converter IRQA Interval timer IRQB Watch FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFE...

Page 114: ...caler Time based timer 8 bit PWM 8 16 bit timer 12 bit MPG 8 bit SIO 10 bit A D converter External interrupt Buzzer output Watchdog timer Re source CPU Main clock Subclock Note RUN SLEEP STOP RUN SLEEP STOP Main mode Sub mode Function Watch Operate Hold Hold Operate Hold Hold Hold A A A A B B A A A A A A B B Operate Operate Operate Operate Operate Operate Operate Operate Operate Operate Operate Op...

Page 115: ...tput P16 to P14 Port input output Port input output Port input output High impedance 2 High impedance P23 P20 Port output Port output Port output High impedance High impedance 6 P22 WDG Port output Port output Port output High impedance High impedance 6 resource output resource output resource output P21 PWO0 Port output Port output Port output High impedance High impedance 6 resource output resou...

Page 116: ...4 1 TRANSFER INSTRUCTIONS 4 3 4 2 OPERATION INSTRUCTIONS 4 4 4 3 BRANCH INSTRUCTIONS 4 5 4 4 OTHER INSTRUCTIONS 4 6 4 5 F2MC 8L FAMILY INSTRUCTION MAP 4 7 4 INSTRUCTIONS ...

Page 117: ...1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 dir A IX off A ext A EP A Ri A A d8 A dir A IX off A ext A A A EP A Ri dir d8 IX off d8 EP d8 Ri d8 dir AH dir 1 AL IX off AH IX off 1 AL ext AH ext 1 AL EP AH EP 1 AL EP A A d16 AH dir AL dir 1 AH IX off AL IX off 1 AH ext AL ext 1 AH A AL A 1 AH EP AL EP 1 A EP EP d16 IX A A IX SP A A SP A T A TH A 1 TL IX d16 A PS PS A SP d16 AH AL dir n 1 dir n 0 AL TL A T A E...

Page 118: ... 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 A A Ri C A A d8 C A A dir C A A IX off C A A EP C A A T C AL AL TL C A A Ri C A A d8 C A A dir C A A IX off C A A EP C A T A C AL TL AL C Ri Ri 1 EP EP 1 IX IX 1 A A 1 Ri Ri 1 EP EP 1 IX IX 1 A A 1 A AL TL A T AL MOD T A A T A A T A A T TL AL T A ...

Page 119: ... 2 2 2 2 3 3 1 3 1 3 1 1 1 if Z 1 then PC PC rel if Z 0 then PC PC rel if C 1 then PC PC rel if C 0 then PC PC rel if N 1 then PC PC rel if N 0 then PC PC rel if V N 1 then PC PC rel if V N 0 then PC PC rel if dir b 0 then PC PC rel if dir b 1 then PC PC rel PC A PC ext vector call subroutine call PC A A PC 1 return from subroutine return from interrupt restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 ...

Page 120: ...9 PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R S 40 50 41 51 00 81 91 80 90 dH NO MNEMONIC TL TH AH N Z V C OP CODE OPERATION SP SP 2 SP A A SP SP SP 2 SP SP 2 SP IX IX SP SP SP 2 No operation C 0 C 1 C 0 C 1 ...

Page 121: ...INSTRUCTIONS 4 7 4 5 F2MC 8L FAMILY INSTRUCTION MAP ...

Page 122: ... OR A R5 OR A R6 OR A R7 CLRI CLRC MOV A T MOVW A T DAA MOV dir d8 MOV IX d d8 MOV EP d8 MOV R0 d8 MOV R1 d8 MOV R2 d8 MOV R3 d8 MOV R4 d8 MOV R5 d8 MOV R6 d8 MOV R7 d8 SETI SETC MOV A A MOVW A A DAS CMP dir d8 CMP IX d d8 CMP EP d8 CMP R0 d8 CMP R1 d8 CMP R2 d8 CMP R3 d8 CMP R4 d8 CMP R5 d8 CMP R6 d8 CMP R7 d8 CLRB dir 0 CLRB dir 1 CLRB dir 2 CLRB dir 3 CLRB dir 4 CLRB dir 5 CLRB dir 6 CLRB dir 7...

Page 123: ...5 MASK OPTIONS ...

Page 124: ...89P147V2 MB89W147V2 5 Single Dual Select when ordering mask Select by EPROM writer Can be selected for each pin Can be selected for each pin Unavailable Unavailable Available for all pins Unavailable Available for all pins Table 5 2 Model Specifications Model SH DIP64 QFP64 MB89PV140 101 MB89PV140C 101 ES SH MB89PV140CF 101 ES MB89PV140 102 MB89PV140C 102 ES SH MB89PV140CF 102 ES MB89144V1 MB89144...

Page 125: ...APPENDIX ...

Page 126: ... Time base timer control register 0BH R W WPCR 00 000 Watch prescaler control register 0CH R W PDR3 XXXX XXXX Port 3 data register 0DH W DDR3 0000 0000 Port 3 data direction register 0EH R W BUZR 00 Buzzer register 0FH R W EIC 0000 0000 External interrupt control register 10H R W PDR4 0000 0000 Port 4 data register 11H R W PDR5 0000 0000 Port 5 data register 12H R W PDR6 0000 0000 Port 6 data regi...

Page 127: ...00 MPG control register 25H R W INTSTR 0000 0000 MPG interrupt status register 26H W CMCLBR H 0000 MPG compare clear buffer register H 27H W CMCLBR L 0000 0000 MPG compare clear buffer register L 28H W OUTCBR H 0000 MPG output buffer register H 29H W OUTCBR L 0000 0000 MPG output buffer register L 2AH 2BH 2CH Reserved Access disable 2DH 2EH 2FH 30H to 77H 78H 79H 7AH 7BH 7CH W ILR1 1111 1111 Inter...

Page 128: ... 2 Load the program data from address 0007H to address 7FFFH of EPROM writer The data is loaded from address 8000H to address 0FFFFH in the operation mode and from address 0000H to address 7FFFH in the EPROM mode Load the option data at addresses 0000H to 0006H in the EPROM writer See the next Bit Map for the corre spondence of each option 3 Write the data with the EPROM writer The memory space in...

Page 129: ...le 0 Unavailable 0 Unavailable 0 Unavailable 0 Unavailable 0 Unavailable possible possible Empty Empty Empty Empty Empty Empty Empty Empty Read write Read write Read write Read write Read write Read write Read write Read write possible possible possible possible possible possible possible possible Empty Empty Empty Empty Empty Empty Empty Empty Read write Read write Read write Read write Read writ...

Page 130: ...32 0 64 0 8 4 0 8 0 8 0 16 0 16 0 32 0 64 0 128 0 16 8 0 16 0 16 0 32 0 32 0 64 0 128 0 256 0 32 16 0 32 0 32 0 64 0 64 0 128 0 256 0 512 0 64 32 0 64 0 64 0 128 0 128 0 256 0 512 0 1024 0 8 MHz 4 MHz 8 MHz 4 MHz 8 MHz 4 MHz 8 MHz 4 MHz µs µs µs µs µs µs µs µs CS1 1 CSO 1 CS1 1 CSO 0 CS1 0 CSO 1 CS1 0 CSO 0 Setting of CS1 and CSO bits system clock select bit of SYCC register Number of system clock...

Page 131: ... Printed in Japan FUJITSU LIMITED Electronic Devices International Operations Department KAWASAKI PLANT 1015 Kamikodanaka Nakahara ku Kawasaki shi Kanagawa 211 Japan Tel 044 754 3753 FAX 044 754 3332 FUJITSU MICROELECTRONICS ASIA PTE LIMITED No 51 Bras Basah Road Plaza By The Park 06 04 to 06 07 Singapore 0718 Tel 336 1600 FAX 336 1609 FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6 10 63303 Dreieic...

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