Fujitsu F2MC-8L Series, Hardware Manual, Page: 33 / 131

HARDWARE CONFIGURATION
2-13
MAIN/SUBCLOCK
CONTROL BLOCK
[Bit 3] TMD: Watch bit
This bit is used to specify switching to the watch mode.
0
1
No operation
Watch mode
Writing at this bit is possible only in the submode (SCS = 0). 0 is always read
when this bit is read. This bit is cleared at an interrupt request or reset.
(2) System clock control register (SYCC)
This register controls the clock for operating the CPU and resources.
SYCC
STBC
Address: 0007
H
Address: 0008
H
Address: 0007
H
Initial value
X--MM100
B
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SCM — — WT1 WT0 SCS CS1 CS0
(R) (R/W) (R/W) (R/W) (R/W) (R/W)
[Bit 7] SCM: System clock monitor bit
This bit is used to check whether the current system clock is the main clock
or subclock.
Subclock (Main clock is stopping or oscillation of main clock stablizing)
Main clock
0
1
[Bits 4 and Bit 3] WT1 and WT0: Oscillation stabilization time select bits
These bit are used to select the oscillation stabilization wait time of the main
clock.
1
1
0
0
Approximate 2
18
/f
CH
Approximate 2
17
/f
CH
Approximate 2
14
/f
CH
Approximate 2
4
/f
CH
1
0
1
0
WT1 WT0 Oscillation stabilization time
Oscillation stabilization time
with 8 MHz source clock
32.8 ms
16.4 ms
2.0 ms
0 ms
f
CH
: Oscillation frequency of main clock
If the main mode is specified by the system clock select bit (SCS), the mode
switches to main mode after the selected wait time has elapsed.
The oscillation stabilization time after resetting is determined by the initial
value.
This bit should not be rewritten during oscillation stabilization or concurrent-
ly with switching of the sub-clock to the main clock.
The oscillation stabilization time for the main clock is generated by dividing
the frequency of the main clock. Since the oscillation cycle is unstable im-
mediately after oscillation starts, the above times should be used as the
standard.