Freetech P5F113, Manual

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Mainboard User’s Manual
48 PnP/PCI Configuration
set to “Disabled,” the ESCD will update automatically when the new
configuration varies from the last one. If set to “Enable,” the ESCD
will be cleared and updated and then this option will automatically be
set to “Disabled.”
IRQ and DMA Assigned to: These fields only become available if
the Resources Controlled By field is set to “Manual.” If there is a
legacy ISA device which uses an IRQ or a DMA, set the correspond-
ing IRQ or DMA to “Legacy ISA”; otherwise, you should set this
field to “PCI/ISA PnP.”
CPU to PCI Write Buffer: When enabled, up to four words of data
can be written to the PCI bus without interrupting the CPU. When
disabled, a write buffer is not used and the CPU read cycle will not
be completed until the PCI bus signals that it is ready to receive the
data.
PCI Dynamic Bursting: When set to “Enabled,” every write trans-
action goes to the write buffer. “Burstable” transactions then burst
on the PCI bus and “nonburstable” transactions do not. The options
are “Enabled,” and “Disabled.”
PCI Master 0 WS Write: When set to “Enabled,” writes to the PCI
bus are executed with zero wait states. The options are “Enabled,”
and “Disabled.”
PCI Delay Transaction: The chipset has an embedded 32-bit posted
write buffer to support delay transactions cycles. Select “Enabled” to
support compliance with PCI specification version 2.1. The options
are “Enabled,” and “Disabled.”
PCI #2 Access #1 Retry: This item allows you enable/disable the
PCI#2 Access #1 Retry.
AGP Master 1 WS Write: This implements a single delay when
writing to the AGP Bus. By default, two-wait states are used by the
system, allowing for greater stability. The options are “Enabled,”
and “Disabled.”
AGP Master 1 WS Read: This implements a single delay when
reading to the AGP Bus. By default, two-wait states are used by the
system, allowing for greater stability. The options are “Enabled,”
and “Disabled.”