Introduction
Chipset
11
2.6. Chipset
The P5F113 supports the VIA 82C598MVP Apollo MVP3 chipset.
The chipset comes in pairs —the North Bridge chip and the South
Bridge chip.
North Bridge
•
CPU interface controller (66/100 MHz FSB)
•
AGP interface controller (AGP 2x)
•
Integrated DRAM controller
(Synchronous 66/100 MHz SDRAM)
•
Fully synchronous PCI 2.1 bus interface
•
Data buffering:
♦
CPU-to-AGP
♦
CPU-to-DRAM
♦
CPU-to-PCI
♦
AGP-to-DRAM
♦
AGP-to-PCI
♦
PCI-to-AGP
♦
PCI-to-DRAM
Southbridge
•
Interface between the PCI and ISA buses
•
Power Management Logic
•
USB controller
•
EIDE controller (ATA33)
•
Seven DMA channels
•
One timer/counter
•
Two 8-channel interrupt controllers
•
NMI logic and SMI interrupt logic
•
PCI/ ISA bus arbitrator
•
SMBus interface
•
Power management Logic
•
Realtime clock (RTC)
•
ACPI controller
This concludes Chapter 2. Chapter 3 covers hardware installation.
Summary of Contents for P5F113
Page 1: ...P5F113 Mainboard Manual Friday March 02 2001 ...
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