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9100A-017
3-4
TRISTATE CONTROL
3.8.
A low signal on the TRISTATE input line of the Vector Output
I/O Module asynchronously tri-states the 40-pin output of the
module. The output of the module remains tri-stated after the
removal of the TRISTATE low signal until a
writeword
or
writepin
command has been executed or further vector driving
has occurred.
If the TRISTATE occurred during vector driving, the proper re-
covery time (txsu) must be met to have the next vector driven
out upon receipt of a clock (see Figure 3-2 and Table 2-1 in
Section 2 of this manual). If the recovery time is not met, the
output of the module remains tri-stated and the current vector is
effectively skipped. To prevent vectors from being skipped,
connect the external ENABLE line to the TRISTATE pin and
use the
enableoutput
mode “high”.
Figure 3-2. TRISTATE Input Timing Diagram
One method of using the external tri-state feature would be when
the Vector Output I/O Module is connected to a peripheral port
on a bus of a UUT. The peripheral select line could be con-
nected to the TRISTATE input of the module. When the port is
not in use, the peripheral select line would tri-state the module.
Summary of Contents for 9100A Series
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Page 14: ...9100A 017 1 4 ...
Page 24: ...9100A 017 3 6 ...
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Page 83: ...A 1 Appendix A New TL 1 Commands ...
Page 84: ...9100A 017 A 2 ...
Page 87: ...clockfreq 3 For More Information The Overview Of TL 1 section of the Programmer s Manual ...
Page 88: ...clockfreq 4 ...
Page 91: ...drivepoll 3 For More Information The Overview Of TL 1 section of the Programmer s Manual ...
Page 92: ...drivepoll 4 ...
Page 104: ...vectordrive 4 ...
Page 107: ...vectorload 3 For More Information The Overview Of TL 1 section of the Programmer s Manual ...
Page 108: ...vectorload 4 ...
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