ZBOQT
A-10.
Bit
Definitions of
Faull Masks
Tables
A—3
through
A-6 describe the
mapping
from specific Z80QT pod signals
to bit positions in the 64-bit
fault
masks generated by the built-in functions when
they invoke
TL
/
l
fault
handlers. In each
format
example,
unmapped
positions
have a “0” value
to maintain
the full mask length
of
64
positions. Positions
labeled “X”
correspondto
mapped signals. Mapped signals have a “1” value
to
indicate an active, faulty,
or
otherwise significant condition.
A
value
of
“0”
represents the absence
of
a significant condition for
that
signal.
Table
A-3.
Address Signal Mapping to Fault Masks
Address signal
fault
mask
format:
"000000000000000000000000000000OOOOOOOOOOOOOOOXXXXXXXXXXXXXXXX"
Bit
63
Bit
15
Bit
0
Address signal
fault
mask
bit
assignments:
Mask
Pod
280
Bit
Signal
Pin No.
0
A0
30
1
A1
31
2
A2
32
3
A3
33
4
A4
34
5
A5
35
6
A6
36
7
A7
37
8
A8
38
9
A9
39
10
A10
40
1
1
A11
1
1
2
A1
2
2
13
A13
3
1
4
A14
4
15
A15
5
16
:
u
nused
63
Summary of Contents for 9000A-Z80QT
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