Z8OQT
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The
pattern
verification test simply verifies
that
memory contains
expected
data.
The test should be used following a normal Quick RAM
test to verify
that
the memory still
contains
the
correctdata
after a longer
period
than
is
checked by the
normal RAM
test. The
pattern
verification
test
is
provided
primarily for testing dynamic RAM memory to assure
that
the memory
retains information
properly. If problems with dynamic
RAM
are suspected, use the
pattern
verification test following the normal
RAM test.
3-17. Quick
ROM Test
Description
The Quick
ROM
test allows the
operator to
test ROM address blocks more
quickly
than
with the
ordinary ROM
test. When the Quick ROM test
is
performed,
the
pod obtains
a checksum
that
may be compared with a checksum
obtained
by
performing
the Quick
ROM
test over the same address block of a
known good UUT. The value
of
this Quick
ROM
test checksum
is
also available
in Table
5-5.
Note
that
this checksum
is
not
the same value
as
the signature
that
is
obtained
with the
ordinary mainframe
ROM test.
The Quick ROM test
is
not as rigorous and reliable
as
the signature analysis used
by the
ordinary ROM
test,
nor
is
error reporting
in the Quick ROM test
as
extensive. However, the Quick
ROM
test can detect inactive
data
bits, and the
checksum can be used
to detect
a
faulty
ROM device with a high degree
of
confidence.
3-18. Using the
9000
Series
for
Quick
RAM
Testing
NOTE
Special addresses
mentioned
in the
followingparagraphs
are also
valid
for
9100 Series mainframes. However, they are
not
necessary
because the 9100 Series
provides
softkeys to directly access these
pod
functions.
The
recommended method
of
running pod-
controlled
quick tests
from
the 9100 Series
is
given
under
a
separate
heading.
Starting
and ending addresses for the Quick RAM test are specified in a different
manner than for
the usual
RAM
test. The
starting
and ending addresses are
specified by writing to special addresses. The
starting
address
is
defined by a
WRITE
@
2X XXXX=0, where X XXXX
is
the address to be used
to start
the
Quick RAM test. The ending address, address increment, and test specification
are defined by a
WRITE
@ 2Y
YYYY=ZN, where
Y
YYYY
is
the desired ending
address, Z
is
the
desired increment, and N
is
the test specification.
Hz
is
omitted
or
specified as 0, the address increment defaults to l. N may be either
1
(normal
Quick
RAM
test)
or
2
(pattern verification
test). The ending address must be
greater than or
equal to the
starting
address.
3-10
Summary of Contents for 9000A-Z80QT
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