FLIR
LEPTON® Engineering Datasheet
The information contained herein does not contain technology as defined by the EAR, 15 CFR 772, is publicly available,
and therefore, not subject to EAR. NSR (6/14/2018).
Information on this page is subject to change without notice.
Lepton Engineering Datasheet, Document Number: 500-0659-00-09 Rev: 203
53
Figure 27 -Clock Too Slow - Failure to Read an Entire Frame Within the Frame Period
Figure 28 - Intra-Frame Delay Too Long - Failure to Read Out an Entire Frame Before the Next is
Available
Figure 29 - Failure to Read Out an Available Frame
4.2.2.3.3
Frame Synchronization
The VoSPI protocol is designed such that embedded timing signals are not required. However, the Lepton does
provide an optional frame-timing output pulse that can aid in optimizing host timing. For example, the host can
burst-read data at a high clock rate and then idle until the next frame-timing pulse is received. The pulse is enabled
by selecting the VSYNC GPIO mode via the CCI; when enabled, it is provided on the GPIO3 pin (see
page
). The signal can be configured (also via the CCI) to lead or lag the actual internal start-of-frame (that is, the
time at which the next frame is ready to be read) by -3 to +3 line periods (approximately -1.5 msec to +1.5 msec).
By default, the pulse does not lead or lag.
