Device
and operation
CPC307
C P C 3 0 7 U s e r M a n u a l
65
© 2 0 2 2 F a s t w e l v . 0 0 6
Table 4.26 provides a detailed description of the WDT0 watchdog timer control registers.
The registers of the timer WDT1 are accessed through the ports 67h - 6Dh.
Table 4.27 provides a detailed description of the WDT1 watchdog timer control registers.
Table 4.26. Description of the WDT0 watchdog timer control registers
Port address
Bit
Access
type
Description
WDT0 Restart Register
65h
7:0
W
Writing to this port will restart the WDT0 timer. Reading is not
possible.
WDT0 Control Register
(value after 40h reset)
Address
register
(22h) = 37h
7
RO
Reserved
6
R/W
WDT0 timer is enabled
0
– disabled
1
– enabled
5:0
RO
Reserved
WDT0 event selection register
(value after D0h reset)
Address
register
(22h) = 38h
7:4
RW
Event selection at the end of WDT0 timer count
Bits [7:4]
– signal:
0000
– reserved
0001
– IRQ[3]
0010
– IRQ[4]
0011
– IRQ[5]
0100
– IRQ[6]
0101
– IRQ[7]
0110
– IRQ[9]
0111
– IRQ[10]
1000
– IRQ[11]
1001
– IRQ[12]
1010
– IRQ[14]
1011
– IRQ[15]
1100
– NMI
1101
– system reset
1110
– reserved
1111
– reserved
3:0
RO
Reserved
Register 0 of WDT0 timer
(value after 00h reset)
Address
register
(22h) = 39h
7:0
R/W
Bits [7:0] of WDT0 timer, resolution
– 30.5
µs
Register 1 of WDT0 timer
(value after 00h reset)
Address
register
(22h) = 3Ah
7:0
R/W
Bits [15:8] of WDT0 timer, resolution
– 30.5
µs
Register 2 of WDT0 timer
(value after 20h reset)
Address
register
(22h) = 3Bh
7:0
R/W
Bits [23:16] of WDT0 timer, resolution
– 30.5
µs
WDT0 state register
(value after 00h reset)
