Device
and operation
CPC307
C P C 3 0 7 U s e r M a n u a l
33
© 2 0 2 2 F a s t w e l v . 0 0 6
4.2.3 Integrated address decoder
The module has two CAN controllers, the SJA1000T and a controller for two RS-232 serial
ports, the XR16C2850IM. These controllers must be assigned with base addresses and address
space ranges prior to their use.
To address these controllers, the Vortex86DX SoC integrated address decoders are used -
the GPCS0, GPCS1 (General Purpose Chip Select) lines. For their work each decoder must
specify a base address, which starts the decoding, and the range of addresses to be covered - the
mask of the base address. These register addresses are located in the I/O area of PCI devices
and are accessible via the PCI configuration registers (CF8h and CFCh).
The GPCS0 base address is Bus 0, Device 7, Function 0, register 90h
GPCS0 address mask - Bus 0, Device 7, Function 0, register 94h
GPCS1 base address - Bus 0, Device 7, Function 0, register 98h
GPCS1 address mask - Bus 0, Device 7, Function 0, register 9Ch
The structure of registers GPCS0, GPCS1 is shown in Table 4.3.
Table 4.3. Structure of GPCS0 and GPCS1 registers
Bit
Name
Attribute
Description
Chip Select 0 Base Address Register
31-1
BA
R/W
Base address,
[31-0] for the memory address range,
[15-1] for the range of I/O addresses
0
EN
R/W
Address decoding authorization
Chip Select 0 Base Address Mask
31-28
Reserved
RO
Reserved
27
RD
R/W
Decoding enabled for read operations on the ISA bus (IOR#,
MEMR#)
26
WR
R/W
Decoding enabled for write operations on the ISA bus (IOW#,
MEMW#)
25
B16
R/W
0
– 8 bit (sampling is active for 8-bit operations)
1
– 16 bit (sampling is active for 16-bit operations)
24
MIO
R/W
0
– decoding during I/O operations
1
– memory address range decoding
23-1
BAM
R/W
Address mask,
[31-9] for memory address range (MIO=1),
[15-1] for I/O operations (MIO-0)
0
Reserved
RO
Reserved
Chip Select 1 Base Address Register
