Device
and operation
CPC307
C P C 3 0 7 U s e r M a n u a l
66
© 2 0 2 2 F a s t w e l v . 0 0 6
Address
register
(22h) = 3Ch
7
R/WC
WDT0 timer status flag
0
– timer was not triggered
1
– timer was triggered (writing “1” to this bit resets the
flag)
6
W
Writing “1” will make the WDT0 timer to restart.
Writing “0” to this bit or reading is not allowed
5:0
RO
Reserved
Table 4.27. Description of the WDT1 watchdog timer control registers
Port address
Bit
Access
type
Description
WDT1 restart register
67h
7:0
W
Writing to this port will restart the WDT1 timer.
Reading is not possible.
WDT1 control register
(value after 00h reset)
68h
7
RO
Reserved
6
R/W
Enabling WDT1 timer operation
0
– disabled
1
– enabled
5:0
RO
Reserved
WDT1
event selection register
(value after 00h reset)
69h
7:4
RW
Event selection at the end of WDT1 timer count
Bits [7:4]
– signal:
0000
– reserved
0001
– IRQ[3]
0010
– IRQ[4]
0011
– IRQ[5]
0100
– IRQ[6]
0101
– IRQ[7]
0110
– IRQ[9]
0111
– IRQ[10]
1000
– IRQ[11]
1001
– IRQ[12]
1010
– IRQ[14]
1011
– IRQ[15]
1100
– NMI
1101
– system reset
1110
– reserved
1111
– reserved
3:0
RO
Reserved
Register 0 of WDT1 timer
(value after 00h reset)
6Ah
7:0
R/W
Bits [7:0] of WDT1 timer, resolution
– 30.5
µs
Register 1 of WDT1 timer
(value after 00h reset)
6Bh
7:0
R/W
Bits [15:8] of WDT1 timer, resolution
– 30.5
µs
Register 2 of WDT1 timer
(value after 00h reset)
