Introduction
CPC307
C P C 3 0 7 U s e r M a n u a l
5
© 2 0 2 2 F a s t w e l v . 0 0 6
Table 5.4:
Description of the “IDE Configuration” menu ...…………………………………………………… .…...90
Table 5.5:
Description of the “Primary IDE Master” menu...…………………………………………..………….…91
Table 5.6:
Description of the “Remote Access Configuration” menu ………………………………………... ..….93
Table 5.7:
Description of the “USB Configuration” menu.……………………………………………..………….…95
Table 5.8:
Description of the “USB Mass Storage Device Configuration” menu.…………………………... ..….96
Table 5.9: Description
of the “PCIPnP” menu …………………………………...…..……….…...….….…………..97
Table 5.10:
Description of the “Boot” menu ……………......…………………………………………………… .…...99
Table 5.11:
Description of the “Boot Settings Configuration” menu.…………………………………..…………...100
Table 5.12:
Description of the “Security” menu……………………….. ………………………………………... ….102
Table 5.13:
Description of the “Chipset” menu …………………………………...…..……….…...….….…………103
Table 5.14:
Description of the “South Bridge Configuration” menu ……………......………………………… .….104
Table 5.15:
Description of the “ISA Configuration” menu…………..…………………………………..…………...106
Table 5.16:
Description of the “Serial/Parallel Port Configuration” menu ..…………………………………... ….107
Table 5.17:
Description of the “WatchDog Configuration” menu .……………………………………..…………...108
Table 5.18:
Description of the “GPIO and I2C Configuration” menu ..………………………………………... ….109
Table 5.19:
Description of the “CAN and COM5,6 Configuration” menu……………………………..…………...111
Table 5.20:
Description of the “Exit” menu…………………………… ..………………………………………... ….112
List of Figures
Figure 2.1: a) Overall dimensions of CPC307 components and their locations (this figure is valid for ver.3x)...20
Figure 2.2: b) Overall dimensions of CPC307 components and their locations (this figure is valid for ver.
4.х)...21
Figure 3.1: Connection of external devices to the CPC307
………………..…………………………….…………..22
Figure 4.1: CPC307 Block Diagram
…………………………………...…………... ……..…………………………...23
Figure 4.2: a) Location of connectors and main components on the TOP and BOTTOM for the CPC307-02,
CPC307-05 versions (valid for CPC307 v.3.x)
…………………………………...……..…………………..………………….…25
Figure 4.3: b) Location of connectors and main components on the TOP and BOTTOM sides of the CPC307-
02, CPC307-05 versions (relevant to CPC307 v.4.x)
………………………………………………………………………....….26
Figure 4.4: a) Location of connectors and main components on the TOP and BOTTOM for the CPC307-03
version (valid for CPC307 v.3.x)
………………………………………………………………………………… .………………..27
Figure 4.5: b) Location of connectors and main components on the TOP and BOTTOM sides for the CPC307-
03 version (valid for CPC307 v.4.x)
…………………………………………………………………………………………..…....28
Figure 4.6: a) Location of connectors and main components on the TOP and BOTTOM for the CPC307-04
version (valid for CPC307 v.3.x)
…………………………………………………...……..…………………..………………….…29
Figure 4.7: b) Location of connectors and main components on the TOP and BOTTOM sides for the CPC307-
04 version (relevant for CPC307 v.4.x)
………………………………………………………………………………………....….30
Figure 4.8: Block diagram of Vortex86DX SoC
.…………………………………………………… .………………..38
Figure 4.9: Numbering of the XP13 connector pins
……………………………………………………………..…....40
Figure 4.10: Numbering pins of the microSD memory card
………………………………………… .………………..41
Figure 4.11: Numbering pins of the XP23 connector
……………………………………………………………..…....42
Figure 4.12: Reset source selection and switching diagram of the opto-isolated input.
………… .………………..43
Figure 4.13: Numbering pins of the XP19 connector
……………………………………………………………..…....43
Figure 4.14: Numbering pins of the XP12 connector
…...…………………………………………… .………………..44
Figure 4.15 Numbering pins of the XP9 connector
……………………………………………………………..…......45
Figure 4.16: Pin assignment of the XP18 connector (for module versions 3.x and lower)
……… .………………..46
Figure 4.17: a) The RS-422/485 transmitter with bias elements and termination resistors (for ver.3.x & lower)...47
Figure 4.17: b) RS-422/485 transmitter with bias elements and with terminating resistors (for 4x versions)
….....48
Figure 4.17: c) Pi
n assignment of the XP18 connector (for module versions 4.х and lower)…… .………………..48
Figure 4.18 Numbering pins of the XP10 and XP16 connectors
………….…………………………………..…......49
Figure 4.19: Connecting several devices via RS-422 Interface
…………………………………… .………………..50
Figure 4.20: Connecting several devices via RS-485 interface
…………………………………… .………………..50
Figure 4.21: Numbering pins of the XP6 and XP7 connectors
………………………………………………………...52
Figure 4.22:
a) Pin assignment of the XP15 and XP20 connectors (for module versions older than 4.х)….….....53
Figure 4.22:
b) Pin assignment of the XP15 and XP20 connectors (for module version 4.х)…….………………..53
Figure 4.23 a) Transmitter with protective bias elements and terminating resistors (for ver. lower than 4.x).......54
Figure 4.23: b) Transmitter with protective bias elements and terminating resistors (for module version 4.x).
…..55
Figure 4.24: Numbering pins of the XP17 connector
…………………………………………………………….….....56
Figure 4.25: Numbering pins of the XP12 connector
…………………………………………..…… .………………..57
Figure 4.26 PCI-104 XS1 connector: a) module top view; b) module bottom view with organizer mounted on the
connector
……………………………………………………………………………….….…………………………………..…......60
Figure 4.27: Numbering the XS2 pins: a) top view of the module; b) bottom view of the module with the organizer
mounted on the connector
…………………………………………………………………….………………… .………………..62
Figure 4.28: a) Pin assignment of the XP4 and XP8 connector (for module versions lower than 4.x)
…..………..63
Figure 4.28:
b) Pin assignment of the XP4 and XP8 connectors for module versions 4.х ………………………...63
Figure 4.29: Numbering pins of the XP5 connector
……….……………………………………………………….......64
Figure 4.30: Connection of the fail-safe biasing on CAN line
……………………………….....…….………………..64
Figure 4.31 Numbering of XP22 connector pins
………………………………………………………………….........76
