54
0
X
FD UART
TO
/
FROM
C
AMERA
L
INK
.
Writing this location sends a byte of serial data to the frame grabber. Reading gets a byte
of serial data and acknowledges its receipt. See the status bit descriptions below for more
information.
0
X
FE
DAC
AND
F
LASH
C
ONTROL
/
F
LASH AND
UART
S
TATUS
.
The Bits are:
Bit 7 Reserved on write, RxData Available on read. When this bit is 1, there is data
available to be read from the UART via register 0xFD. The validity of the current data
depends on the error bits listed below. This and other receive status bits are cleared when
the UART is read.
Bit 6 "Fget8" on write, Transmitter Ready on read. Writing this bit to one starts the
sequencer for speeding up flash read and FPGA configuration write. Writing this bit to
zero has no effect. When 1 this bit indicates that the UART is ready to accept a byte of
data to transmit to the frame grabber.
Bit 5 DAC chip select on write, Receiver framing error on read. DAC chip select is
asserted high. This bit is inverted before driving the chip's active low pin. Receiver
framing error indicates that a zero was detected in the stop bit position. This condition is
cleared when the UART is read.
Bit 4 DAC serial clock on write, Receiver overrun error on read. DAC serial clock runs
directly to the DAC chips. Receiver overrun indicates that a new character came in when
the previous character had not been read. In this case the older data is lost and the data
in the UART is the one causing the overrun, i.e. the most recent character received. This
condition is cleared when the UART is read.
Bit 3 Flash chip select on write, Transmit overrun on read. Flash chip select is asserted
high. This bit is inverted before driving the chip's active low pin. Transmit overrun is set if
a write was attempted when the transmitter wasn't ready for data. This condition is cleared
when data is written to the UART and the transmitter is ready for data.
Bit 2 Flash reset on write, transmitter empty on read. Flash reset is asserted high. This
bit is inverted before driving the chip's active low pin. Transmitter empty is active when no
data transmission is pending. This must be checked before changing the baud rate to
ensure any pending characters finish transmitting at the current baud rate.
Bit 1 Flash serial clock on write, Flash ready on read. These correspond directly to the
flash pin functions.
Bit 0 Shared Flash and DAC serial data in on write, Flash data out on read. These
correspond directly to the respective pin functions.
