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To simplify command processing, commands that are handled in the Control FPGA are
assigned in ascending order starting with "G," and commands for the Data FPGA are
assigned in descending order starting with "Z."
G
ET
C
AMERA
S
TATE
This command takes no arguments. The camera responds with "G" followed by the
current running state of the camera (512 bytes as 1024 hex digits) and a carriage-return.
This can be used to synchronize the GUI with the camera at initial connection time.
Camera state is sent as hex ASCII unlike the flash page read. This is because the camera
state is a single page worth of data, but flash page read is likely to be used many times in
a row to read large amounts of data such as the FPGA bit-stream.
P
ING
C
AMERA
This command takes no arguments. The camera responds with "H" followed by eight hex
digits and a carriage-return. The eight hex digits indicate the value of a free-running 32-bit
frame counter. This counter indicates all frames read from the sensor since power on, not
necessarily the number of frames sent to the frame grabber. The number of grabbed
frames depends on the memory functions such as frame binning, FIFO and circular
buffering. Successive pings can be used for a rough estimate of the sensor frame rate.
R
ESTORE
C
AMERA
S
TATE FROM
F
LASH
This command takes one argument. The argument can be 01 to 08 and indicates which of
the 8 flash storage areas to retrieve the camera settings from. If the flash storage area is
un-initialized the camera will send a negative acknowledge. Otherwise the camera
responds with "I" followed by the flash storage area number and a carriage-return. The
Restore Camera State from Flash command only restores user settable parameters other
than the Data FPGA loads.
I
NITIALIZE
FPGA
FROM
F
LASH
This command takes no arguments. The Data FPGA is reloaded from the flash causing a
complete re-initialization of the readout logic. If the FPGA fails to load for any reason, the
camera will send a negative acknowledge and response code. Otherwise the camera
responds with "J" followed by a carriage-return. Failure results when the DONE signal
does not go high after download, or if the INIT# signal is reasserted after the bit-stream
has started to load. Either of these conditions indicates a bit-stream error. The Control
FPGA does not check the bit-stream for correct format or CRC; this is done by the FPGA.
To reduce the timeout length if the J command is issued when the flash is un-initialized;
the bit-stream bit counter only loads the low 24 bits of the bit-stream length from the flash
header. This still allows up to 128 megabits of bit-stream, larger than the flash size. On
error a response code is returned. The first byte is the reason which may be 00 01 or 02.
00 indicates bad header flash part type. 01 indicates illegal starting page address. 02
indicate load was attempted but did not complete. If the code is 02, six additional bytes
