53
4
response to a serial trigger command
Bit
3
Reserved.
Bit
2
Calibrate sensor. This is a pulsed signal that schedules a calibration when this
bit is written to 1. Writing this bit to zero has no effect. Actual calibration may
happen much later, since the sensor control logic schedules calibration only
between frames.
Bit
1
Sensor standby. Setting this bit to one places the sensor in low-power
standby mode
Bit
0
Dark offset enable. Setting this bit allows the sensor to apply internal
calibration factors to reduce fixed column noise.
0
X
FB A
DDRESS
E
XTENSIONS
.
Bits 3 through 7 are reserved. Other bits are:
Bits 2, 1, 0
Banking bits. These bits form the two high address bits to the 1K byte data
RAM, except during register access. During register access the high bits are fixed at 6,
thus register writes are always shadowed in the 7th of 8 banks, allowing read back of
registers that don't have separate read functionality from the shadow RAM. When bank 0
is selected, sensor register write is enabled.
0
X
FC S
ERIAL TO
FPGA
AND
S
ERIAL
S
TATUS
.
When written, this register causes a byte of data to be transmitted to the Data FPGA. On
reads Bits 0 through 3 are reserved. Other bits are:
Bit 7 Transmitter to FPGA ready for data.
Bit 6 Transmitter to FPGA overrun error. Set if write was attempted when the transmitter
wasn't ready for data. Cleared when the next data is written when the transmitter is ready
for data.
Bit 5 Transmitter to USB host busy (transmit data available). Set when the PicoBlaze
writes to offset 0x61 in the USB shared area (page 7). Cleared when the data is read by
the USB host via I2C.
Bit 4 Receiver from USB host has data available. Set when the USB host writes to sub
address 0x60 via I2C. Cleared when the data is read by the PicoBlaze at offset 0x60 in
the USB shared area.
