49
This command can take no arguments or it can take a 32-bit (8 hex digits) address. This
command is only effective in the memory readout modes. If enabled, the CC2 line will also
initiate this command allowing operation without the GUI. The Data FPGA will respond
with "Y" followed by a carriage-return.
R
ESET
M
EMORY
This command takes no arguments. This command is only effective in the memory
readout modes. If enabled, the CC3 line will also initiate this command allowing operation
without the GUI. The Data FPGA will respond with "Z" followed by a carriage-return.
Inter-FPGA Communications
S
ERIAL
C
OMMANDS
Commands from the host are buffered and passed to the Data FPGA on the FPGA_CTL3
wire. The Data FPGA therefore receives all commands from the host and can act on them
accordingly. This allows extensions to be made to the command set for Data FPGA use.
To reduce logic in the Data FPGA, each character is buffered and retransmitted at 66
MHz, synchronous to the FPGA_SYSCLK. In this way the data FPGA doesn't need to
know about baud rate and can start up monitoring commands even before it receives the
camera state data.
F
LASH
D
ATA
In addition to forwarding commands from the host, the Control FPGA also uses the
FPGA_CTL3 wire to send camera state data when the Restore Camera State from Flash
command is received. It also uses the FPGA_CTL3 wire to send camera state data and
Data FPGA initialization data from flash to the Data FPGA when the Initialize FPGA from
Flash command is received. The Control FPGA only responds to the host after it has
completed the required data transfer(s). The host must always wait until it receives the
response before sending another command.
When transmitting camera state data to the Data FPGA, the Control FPGA uses the same
syntax as the Set Camera State command with the starting address set to zero and a data
length of 512.
When transmitting Data FPGA initialization data to the Data FPGA, the Control FPGA uses
the same syntax as the Set Camera State command with the starting address set to all
ones (65,535) and a data length as set in the Page Zero Flash Header. If the header
indicates a zero data length, or the initialization data does not start with 3C A5 0F 96, the
Control FPGA will not send this command.
S
ERIAL
R
ESPONSES
