Functional Description
ComTec GmbH
4-3
Since the maximum ADC data rate is comparably slow a smaller ADC event FIFO of 320 events
is sufficient.
On the other hand a high average count rate must be stored without loss of events. The decoding
and binary time coding of the raw data as buffered in the first FIFO stage is accomplished at a
rate of over 33 MHz. Since the bandwidth of the USB 2.0 transmission is limited to something like
35 MB/s a large second FIFO is provided that is able to store a high number of data.
NOTE:
Since September 2015 a new Firmware v 14 can be downloaded from
www.fastcomtec.com
that
uses 3 decoding machines parallel and increases the rate to fill the large FIFO from 33 MHz to
100 MHz
!
The optional up to 2 GB large DDR2 FIFO is designed to be used in an optimized way depending
on the number of bytes that is transferred for each single event. I.e. for 64 bit = 8 byte data words
up to 2 GB / 8 = 256 Mevents can be buffered. The same is true for 48 bit = 6 byte words. For
32 bit = 4 byte data up to 512 Mevents, for 16 bit = 2 byte data up to 1 Gevents can be stored in a
2 GB DDR2 module.
Fig. 4.2: FIFO concept