ETAS
Technical Data
FETK-S2.1 - User’s Guide
37
7.7
JTAG Timing Characteristics
The following diagrams show the timings the FETK-S2.1 can process.
7.7.1
JTAG Timing Diagram
7.7.2
JTAG Timing Parameters
NOTE
JTAG timing parameters in this chapter refer to the JTAG interface (CON1) of
the FETK-S2.1. The JTAG wiring to the ECU (ETAM8) must be taken into
account additionally.
All timings are measured at a reference level of 1.5 V. Output signals are mea-
sured with 20 pF to ground and 50
to 1.5 V.
Parameter
Symbol
Value [ns]
Comment
JTAG Clock Period
(ETK --> Target)
t
tck
50
20 MHz Nexus JTAG
Clock Frequency
25
40 MHz Nexus JTAG
Clock Frequency
20
50 MHz Nexus JTAG
Clock Frequency
TMS/TDI Set-Up Time
(ETK --> Target)
t
setup
7 (min.)
Minimum 5 ns required
for microcontroller
TMS/TDI Hold Time
(ETK --> Target)
t
hold
7 (min.)
Minimum 5 ns required
for microcontroller
TDO clock-to-out time
(Target --> ETK)
t
do_min
2.25 (min.)
Minimum 2.25 ns
required by microcontrol-
ler specification
t
do_max
16 (max)
Maximum 16 ns by
microcontroller specifica-
tion
