ETAS ES5340.2, User Manual

Page: 39 / 120

ES5340.2 Electric Drive Simulation Board -User’s Guide 39
ETAS Hardware Description
Signal Generation
The configuration of the digital outputs can be done in the RTIO editor by the
item „ES5340-Digital-Out-Mux“ (see
"Output Multiplexers for the Digital
Signals" on page 41 ).
A schematic diagram for a digital output is shown in Fig. 3-6 on page 39.
S1 is a slow switch to select the "Output Mode".
S3 is a slow switch to cut off the signal.
S2 is a fast low-side switch to generate the output signal "Digital Output i" in
real-time. In doing so, S3 is closed.
Generation of a digital output signal "Digital Output i":
• The signal that is set in the "Signals" tab through "Output Select" deter-
mines the cycle time for S2.
• The pull-up resistor determines the voltage level of the signal. In the col-
umn "Output Mode" in the "Signals" tab, you can choose between an
internal pull-up resistor ("Pull-Up to +5 V") and an external pull-up resis-
tor ("Open Collector"), see Fig. 3-6.
• By closing S2, the low-phase of the signal is generated. By opening S2, the
high-phase is generated.
Fig. 3-6 Schematic circuit diagram of a digital output
ECU
5 V Supply
Digital
Output i
Common
GND
+
-
FPGA
S1
S2
S3
ECU
5 V Supply
Digital
Output i
Common
GND
+
-
FPGA
S1
S2
S3
0...60 V
Output Mode: Pull-Up to +5 V
Output Mode: Open Collector