Erbe ICC 200, Service Manual

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3 CIRCUIT DESCRIPTION
Art. No.: 801
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4
QC power stage
Slot J4
This charge cannot then flow back into the actuation circuit after the actuation pulse has ended, since diode
D8 acts as a block and diode D9 also permits no reverse current due to its Z-diode characteristic. The result
is that the transistor remains in a conducting state as long as its GS capacitance has sufficient charge.
If, on the other hand, a sufficiently large negative pulse comes from the actuation circuit, the Z-diode
voltage at diode D9 is exceeded and the GS capacitance can be discharged again. Transistor T1 thereby acts
as a block.
It can thus be seen that a MOS-FET transistor can be operated in switching mode via such a clamping
circuit by means of a pulse transformer with short start and stop pulses.
Capacitors C4 and C5 are connected in parallel to the GS capacitance and support the effect described.
Since their capacitance is significantly higher than the corresponding gate-source capacitances, the circuit
becomes largely independent of parameter scatter of the gate-source capacitances of different production
batches.
It is the task of actuation to time the actuation process in such a way that each of the two power transistors
receives a short start pulse and, after a defined pause, a stop pulse at the right time. It must be ensured that
the two transistors are never switched to a conducting state simultaneously, since a short circuit of the
supply voltage would result!
Circuit description
The actuation signals are generated on the control board (30128-357). These signals are short pulses for
starting and stopping the output stage transistors and two additional pulses, one for selecting the upper
output stage transistor and the other for selecting the lower output stage transistor.
These pulses come via connector J1 to the NAND gates ½ IC1 and IC4 on the QC board. There the "Start"
and "Transistor A" pulses, for example, are brought together (as are "Stop" and "Transistor A"). The following
pulse sequences are thus present at the outputs of IC 1:
• Start transistor A
• Stop transistor A
• Start transistor B
• Stop transistor B.
These pulses are each preamplified in the triply parallel gates of the NOR circuits IC 2 and IC3. The outputs
of IC2 and IC3 actuate the driver stages, each consisting of two parallel transistors T3 to T10. The output
signal of the four parallel drivers is then amplified to such a level that the pulse transformers UE1 and UE2
can be operated with sufficient energy.
In the case of a complementary output stage, it must be strictly ensured that the two output stage transistors
are not simultaneously in the activated state, as this would cause a short circuit across the two transistors
and damage the output stage beyond repair.
Therefore, the stop pulses generally have the highest priority. They ensure a safe state of the output stage
during undefined operation. The start pulses are separated in the actuation logic to ensure that only one
output stage transistor is actuated at any one time.
An undefined state could, however, occur in rare cases if the +15 V operating voltage is too low at any point