Erbe ICC 200, Service Manual

Page: 143 / 266

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3 CIRCUIT DESCRIPTION
Art. No.: 801
16-201
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9
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4
CPU board
Slot J1
The following functions are located on the PCB:
• The CPU with RAM and EPROM
• The clock generator
• The voltage supply monitor
• The digital input and output via Parallel Input/Output modules (PIO)
• Analog inputs via an A/D converter
• The Chipselect generation
• The safety interlock signal for controlling the activation signals.
As the central processing unit (CPU), the CMOS microprocessor Z84 C00 (IC1) is used together with the
EPROM 27 C 512 as the program memory (IC3) and the battery-buffered RAM 5864 as the main memory
and constant memory (IC2)
The clock pulse for operation of the computer is produced in the quartz clock generator IC16 and then processed
in the two D-flipflops IC13 to a half-frequency, counterphase clock.
In case of a breakdown of the supply voltage, the current computer data must still be “saved” and stored in the
battery-buffered RAM. All these tasks are supported by the supervisor circuit IC10 (MAX 691).
The supply voltage is monitored via the resistor voltage divider R3, R4 and the “Powerfail” input (Pin 9,
IC10). The data are buffered by a 3 volt lithium battery BT1 which is connected at Pin 1 of the IC10. The
circuit also monitors the voltage of this buffer battery. When switching on, the circuit affects a reset of the
computer system to a specific initial status and provides the monitoring and functional capability through an
integrated “watchdog” circuit.
In addition, the +5 volt supply voltage is also monitored in a separate circuit via resistor R9, diode D1, buffer
capacitor C13 and resistor R7 via the PIO IC6, Pin 27.
The digital inputs and outputs of the computer are taken care of by the Parallel Input/Output circuits (PIOs,
IC4 to IC7). The input and output ports are specified and connected by the program.
Analog dimensions, processed by the processor, move via the level adaptation (resistor network RN1, resistors
R15 to R18) and simultaneous low-pass (capacitors C16 to C19) to the 4-channel analog-digital converter
IC14, from whence the data are available to the processor.
Since all system data are present together at the databus, the system must be able to address the target modules
to which the data apply. This occurs in a processor system by means of the Chipselect lines by which very
specific modules can be addressed via the assistance of “selection signals”.
The Chipselect signals are created in the decoder IC9 from the addresses A3, A4 and A5. Depending on the
address, only one output line each is switched to logical low.
All signals from the various fingerswitches and footswitches are summarized and verified in a safety interlock
signal as to whether any impermissible overlappings or impermissible conditions are produced. If no
impermissible overlappings are determined, the safety interlock signal generates a signal which identifies the
passed on data as save. This logic is accepted by the programmable controller IC17.