Epson S1D16000 Series Technical Manual Download Page 28

Page: 28 / 86

S1D16400 Series

2–4

EPSON

5. PAD LAYOUT

100

105

(0,0)

Chip size ............................ 11.59mm x 1.40mm
Pad pitch ............................ 105

m (Min.)

Chip thickness .................... 625

Au bump specification (S1D16400D00B

) reference values

Bump size

160

(Pad No. 2 ~ 26)

Bump size

(Pad No. 1, 27, 37 and 98)

Bump size

(Pad No. 28 ~ 36 and 99 ~ 107)

Bump size

(Pad No. 38 ~ 97)

Bump height A ~ D

22.5

5.5

(Pad No. 1 ~ 107)

www.DataSheet4U.com

Summary of Contents for S1D16000 Series

Page 1: ...D16000 Series EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION First issue November 1990 Printed May 2001 in Japan H A 4 5mm This manual was made with recycle paper and printed using soy based inks Technical Manual LCD DRIVERS S1D16000 Series http www epson co jp device www DataSheet4U com ...

Page 2: ...or circuit and further there is no repersesnation that this material is applicable to products requiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of...

Page 3: ...CP Model number Model name D LCD Driver Product classification S1 Semiconductors Comparison table between new and previous number Previous number New number SED1606D0A S1D16006D00A SED1606D0B S1D16006D00B SED1606F0A S1D16006F00A SED1606D1A S1D16006D01A SED1606D1B S1D16006D01B SED1640D0B S1D16400D00B SED1651D0A S1D16501D00A SED1670D0A S1D16700D00A SED1670D1A S1D16700D01A SED1670D0B S1D16700D00B SED...

Page 4: ...CONTENTS S1D 16000 series Selection Guide Segment drivers S1D 16006 1 1 S1D 16400 2 1 Common drivers S1D 16501 3 1 S1D 16700 4 1 S1D 16702 5 1 www DataSheet4U com ...

Page 5: ...Selection Guide www DataSheet4U com ...

Page 6: ...o 5 5 8 to 28 S1D16700D00B SED1670D0B S1D16700D01B SED1670D1B S1D16702D00A SED1672D0A S1D16702D01A SED1672D1A S1D16702D00B 2 7 to 5 5 8 to 28 SED1672D0B S1D16702D01B SED1672D1B S1D16702F00A SED1672F0A Al pad chip zigzag positioning Al pad chip INH type Al pad chip DOFF type Au bump chip INH type Au bump chip DOFF type Al pad chip INH type Al pad chip DOFF type Au bump chip INH type Au bump chip DO...

Page 7: ...S1D16006 Series Rev 2 1 www DataSheet4U com ...

Page 8: ...AGRAM 1 2 4 PIN DESCRIPTION 1 3 5 PAD 1 4 6 PIN LAYOUT 1 6 7 FUNCTIONAL DESCRIPTION 1 7 8 TIMING CHART 1 8 9 ABSOLUTE MAXIMUM RATINGS 1 9 10 ELECTRICAL CHARACTERISTICS 1 10 11 LCD DRIVE POWER 1 13 12 TYPICAL CIRCUIT DIAGRAM 1 14 Rev 2 1 www DataSheet4U com ...

Page 9: ...applications 2 FEATURES Number of LCD drive output segments 80 Low current consumption Low voltage operation 2 7 V Max Wide range of LCD drive voltages 8 V to 28 V High speed and low power data transfer enabled by means of a 4 bit bus and chain enable support Shift clock frequency 6 5 MHZ at 2 7 V 10 0 MHZ at 4 5 V Selectable pin output shift direction S1D16006D01A Adjustable offset bias of LCD po...

Page 10: ... V D3 to D0 SHL EIO1 EIO2 XSCL LCD driver 80 bit Level shifter 80 bit Enable shift register Latch 80 bit Data register 80 bit DSPOFF SS DD 1 Dummy terminal NC when S1D16006D00 is used DSPOFF terminal when S1D16006D01 is used 1 3 BLOCK DIAGRAM www DataSheet4U com ...

Page 11: ...p between the data and segment output is determined irrespective of the number of shift clock inputs LCD drive output AC converted signal input Force input of blank V0 level is forcibly set by entering LOW level available with S1D16006D01 alone Logic power supply VDD 0 V VSS 2 7 V to 5 5 V LCD drive circuit power supply VDD 0 V V5 8 V to 28 V VDD V0 V2 6 9 V5 3 9 V5 V3 V5 When used at a same poten...

Page 12: ...AL pad die form 0 525 mm Au bump die form Au bump specifications Reference values Bump size 117µm 109µm 20 um Bump height 17µm to 28µm Details shall be stipulated in the delivery specification AL pad die form Pad Opening 87 76µm 0 0 Y X 75 50 65 80 60 70 55 85 90 95 100 1 5 10 15 20 25 30 35 40 45 D1606D0B www DataSheet4U com ...

Page 13: ... 79 O78 2073 80 O79 2227 81 EIO2 2381 82 D0 2622 1346 83 D1 1192 84 D2 1039 85 D3 885 86 Dummy 732 87 Dummy 578 88 Dummy 424 89 1 271 90 VDD 106 91 VSS 58 92 V0 224 93 V2 389 94 V3 553 95 V5 718 96 SHL 2611 885 97 XSCL 1039 98 LP 1192 99 FR 1346 100 EIO1 2381 1578 PAD Actual dimensions NO NAME X Y 35 O34 2622 871 36 O35 713 37 O36 554 38 O37 396 39 O38 238 40 O39 79 41 O40 79 42 O41 238 43 O42 396...

Page 14: ... O50 52 O51 53 O52 54 O53 55 O54 56 O55 57 O56 58 O57 59 O58 60 O59 61 O60 62 O61 63 O62 64 O63 65 O64 66 O65 67 O66 68 O67 69 O68 70 O69 71 O70 72 O71 73 O72 74 O73 75 O74 76 O75 77 O76 78 O77 79 O78 80 O79 81 EIO2 82 D0 83 D1 84 D2 85 D3 86 NC 87 NC 88 NC 89 1 90 VDD 91 VSS 92 V0 93 V2 94 V3 95 V5 96 SHL 97 XSCL 98 LP 99 FR 100 EIO1 PIN No NAME PIN No NAME PIN No NAME PIN No NAME PIN No NAME S1D...

Page 15: ...al using the control LSI Data register This is a register used to convert the data bus signal into serial or parallel signal through the enable shift register output Consequently the relationship between the serial display data and segment output is determined irrespective of the number of shift clock inputs Latch This latch is used to fetch the content of data register at the LP falling edge trig...

Page 16: ...3 EIO 1 EIO 2 FR V0 V2 V3 V5 H H H L L L L H H L L H H H H L L L 20 1 2 3 1 2 3 20 1 2 3 1 2 3 20 20 200 200 199 1 2 1 200 199 1 2 3 4 When the duty is 1 200 Reference Example S1D16006D00 S1D16006D01 When S1D16006D01 is used The driver output is forcibly switched to V0 output upon switching of DSPOFF 8 TIMING CHART www DataSheet4U com ...

Page 17: ...ermanent damage to the LSI Functional operation under these conditions is not implied Care should be taken to the power supply sequence especially in the system power ON or OFF Parameter Symbol Rating Unit Power voltage 1 VSS 7 0 to 0 3 V Power voltage 2 V5 30 0 to 0 3 V Power voltage 3 V0 V2 V3 V5 0 3 to VDD 0 3 V Input voltage VI VSS 0 3 to VDD 0 3 V Output voltage VO VSS 0 3 to VDD 0 3 V EIO ou...

Page 18: ... 0 4 Typ 5 0 1 2 0 10 0 07 0 05 Max 2 7 12 0 8 0 VDD 6 9V5 0 8VSS VSS 0 4 2 0 5 0 25 1 6 0 2 0 15 0 08 8 15 Unit V V V V V V V V V V µA µA µA kΩ mA mA pF pF Applicable pin VSS V5 V5 V0 V2 V3 EIO1 EIO2 FR D0 to D3 XSCL SHL LP EIO1 EIO2 D0 to D3 LP FR XSCL SHL EIO1 EIO2 VSS O0 to O79 VSS V5 D0 to D3 LP FR XSCL SHL EIO1 EIO2 Parameter Supply voltage 1 Recommended operating voltage Operation enable vo...

Page 19: ...CL HIGH pulsewidth tWCH 50 ns XSCL LOW pulsewidth tWCL 50 ns Data setup time tDS 30 ns Data hold time tDH 15 ns XSCL rise to LP rise time tLD 0 ns VSS 2 7V 75 LP fall to XSCL fall time tLH ns VSS 3 0V 65 VSS 2 7V 3 75 LP HIGH pulsewidth tWLH ns VSS 3 0V 3 65 Allowable FR delay time tDF 900 900 ns VSS 2 7V 60 EIO setup time tSUE ns VSS 3 0V 51 1 Equivalent to 6 5 MHz 2 Equivalent to 7 5 MHz 3 tWLH ...

Page 20: ...ut delay time tLSD 200 ns CL 100pF On FR to SEG output delay time tFRSD 400 ns VDD 4 5V to 2 7V V5 12 0 to 28 0V Parament Symbol Condition Min Max Unit EIO reset time tER 150 ns CL 15pF VSS 2 7V 88 ns EIO output delay time tDCL EIO VSS 3 0V 77 ns LP to SEG output delay time tLSD 400 ns CL 100pF On FR to SEG output delay time tFRSD 800 ns 1 tr and tf of input signal are stipulated by unit of 20 ns ...

Page 21: ...cases When a protection resistor is inserted it is necessary to stabilize the voltage by capacitance Note in power ON OFF Since this LSI is high in the voltage of LCD driving system when a high voltage is applied to the LCD driving system with the logic system power supply kept floating or above VSS 2 6 V and when the LCD driving signal is output before the applied voltage to the LCD driving syste...

Page 22: ...L0 to 3 DI01 DI02 DI01 DI02 S1D16700 S1D16700 80 80 S1D16006 S1D16006 S1D16006 EI01 V DD EI02 EI01 EI02 EI01 8 2 1 EI02 640 200 DOT 1 200 DUTY r r R r r V0 V1 V2 V3 V4 V5 V5 VSS VDD 100 100 12 TYPICAL CIRCUIT DIAGRAM Configuration Drawing of Large Screen LCD www DataSheet4U com ...

Page 23: ...S1D16400 www DataSheet4U com ...

Page 24: ...2 4 FUNCTIONS OF THE TERMINALS 2 3 5 PAD LAYOUT 2 4 6 PAD CENTER COORDINATES 2 5 7 FUNCTION DESCRIPTIONS 2 6 8 ABSOLUTE MAXIMUM RATING 2 7 9 ELECTRICAL CHARACTERISTICS 2 8 10 REGARDING THE LCD DRIVING POWER 2 12 11 AN EXAMPLE OF CONNECTION 2 13 www DataSheet4U com ...

Page 25: ...ations 2 FEATURES LCD driver output number 80 Ultra slim chip Low current consumption Low voltage operation 2 7V Max Wide range of liquid crystal drive voltage 8 to 28V High speed and low power data transfer is possible by adoption of the 4 bit bus inable chain system Shift clock frequency 6 5MHz at 2 7V 7 5MHz at 3 0V Non bias display off function Pin selection of the output shift direction is av...

Page 26: ...es 2 2 EPSON O 0 O79 V0 V2 V5 V3 FR LP DSPOFF V V D0 to D3 SHL EIO1 EIO2 XSCL LCD driver 80 bit Level shifter 80 bit Inable shift register Latch 80 bit Data register 80 bit SS DD 3 BLOCK DIAGRAM www DataSheet4U com ...

Page 27: ...erminals in the order of a b c d e f g h w x y z relations between data and segment outputs are as follows Note Relations between data and segment outputs are determined independent from the shift clock number FR I Input of the alternating signal of the LCD drive output 1 VDD VSS Power Power supply for the logics VDD 0V 3 source VSS 2 7 5 5V V0 V2 Power Power supply for the LCD driver circuit 8 V3...

Page 28: ...m Pad pitch 105µm Min Chip thickness 625µm 25µm Au bump specification S1D16400D00B reference values Bump size A 160µm 80µm 4µm Pad No 2 26 Bump size B 86µm 91µm 4µm Pad No 1 27 37 and 98 Bump size C 86µm 68µm 4µm Pad No 28 36 and 99 107 Bump size D 82µm 74µm 4µm Pad No 38 97 Bump height A D 22 5 5 5µm Pad No 1 107 www DataSheet4U com ...

Page 29: ...4197 45 O17 4019 46 O18 3840 47 O19 3661 48 O20 3483 49 O21 3304 50 O22 3126 51 O23 2947 52 O24 2768 53 O25 2590 54 O26 2411 55 O27 2233 56 O28 2054 57 O29 1875 58 O30 1697 59 O31 1518 60 O32 1340 61 O33 1161 62 O34 982 63 O35 804 64 O36 625 65 O37 447 66 O38 268 67 O39 89 68 O40 89 69 O41 268 70 O42 447 71 O43 625 72 O44 804 73 O45 982 X axis of Y axis of PAD NO PAD NAME coordinates coordinates 2...

Page 30: ...ple of the connection Since the inable control circuit automatically detects when all the 80 bit data are taken in and automatically transfers the inable signal control signals from a controlling LSI are not needed Data registor This is a registor for serial and parallel conversion of data bus signals by means of the inable shift registor output Consequently the relations between the serial displa...

Page 31: ...BSOLUTE MAXIMUM RATING Note 1 All the above voltage is based on VDD 0V Note 2 The storing temperature 1 specifies that of chips proper and the storing temperature 2 specifies that of TAB packages Note 3 Voltage of V0 V2 and V3 should always be maintained under a condition of VDD V0 V2 V3 V5 Note 4 When logic power becomes floating state or if VSS 2 6 or beyond while the LCD driver power source is ...

Page 32: ...4 V voltage Input leak current ILI VSS VIN VDD D0 D3 LP FR 2 0 µA XSCL SHL DSPOFF Input and output ILI O VSS VIN VDD EIO1 EIO2 5 0 µA leak current Rest current ISS V5 28 0 14 0V VSS 25 µA VIH VDD VIL VSS Output resistance RSEG VON 0 5V O 0 O 79 1 5 2 5 kΩ V5 20 0V V3 13 15 V5 V2 2 15 V5 V0 VDD Average operating ISS VSS 5 0V VIH VDD VSS 0 10 0 2 mA current VIL VSS fXSCL 2 69MHz consumption 1 fLP 16...

Page 33: ...SCL 20 1 2 3 20 1 2 3 20 1 3 2 1 20 D0 to D3 EIO 1 EIO 2 EIO n 1 2 Timing Diagram In case of 1 200 duty an example 1 n indicate the cascade numbers of drivers In case of high speed data transfer it is necessary to secure a longer XSCL cycle in the timing of the LP pulse insertion in order to maintain the specified value of LP XSCL tLH www DataSheet4U com ...

Page 34: ...me tSUE ns VSS 3 0V 40 1 6 5MHz equivalence 2 7 5MHz equivalence 3 twLH specifies the time when LP is HIGH and at the same time XSCL is LOW 1 2 3 3 VSS 5 0V 0 5V Ta 40 85 C Items Symbols Conditions Min Max Unit XSCL cycle tC 100 ns XSCL HIGH level pulse duration tWCH 30 ns XSCL LOW level pulse duration tWCL 30 ns Data setup time tDS 30 ns Data hold time tDH 20 ns XSCL LP rise time tLD 0 ns LP XSCL...

Page 35: ... ns CL 100pF 0n FR SEG output delay time tFRSD 400 ns VDD 4 5V 2 7V V5 12 0 28 0V Items Symbols Conditions Min Max Unit EIO reset time tER 150 ns CL 15pF VSS 2 7V 95 ns EIO output delay time tDCL EIO VSS 3 0V 85 ns LP SEG output delay time tLSD 400 ns CL 100pF 0n FR SEG output delay time tFRSD 800 ns tDCL FR LP XSCL EIO1 2 OUT SEG tER tLSD tFRSD Output timing characteristics www DataSheet4U com ...

Page 36: ...t becomes unable to maintain the relations of the LCD with intermediate potentials VDD V0 V2 V3 V5 leading to breakage of the LSI When installing protective resistors it is necessary to stabilize the voltage by their capacity Cautions when turning the power on and off Since the LCD drive system voltage with this LSI is comparatively high when high voltage is applied to the LCD drive system leaving...

Page 37: ...r r VSS DL0 to 3 V2 V3 V4 V5 VDD V5 F R D D 1 2 8 1 2 0 0 D U T Y 100 100 S1D16700 S1D16700 DIO1 DIO2 DIO1 DIO2 80 80 S1D16400 S1D16400 EIO1 EIO1 EIO2 EIO2 S1D16400 EIO1 EIO2 80 6 4 0 2 0 0 D O T 11 AN EXAMPLE OF CONNECTION Block diagram of a large sized LCD www DataSheet4U com ...

Page 38: ...S1D16501 Rev 1 0 www DataSheet4U com ...

Page 39: ...3 BLOCK DIAGRAM 3 2 4 PIN DESCRIPTION 3 3 5 PAD 3 4 6 FUNCTIONAL DESCRIPTION 3 6 7 TIMING CHART 3 7 8 ABSOLUTE MAXIMUM RATINGS 3 8 9 ELECTRICAL CHARACTERISTICS 3 9 10 LCD DRIVE POWER 3 12 11 TYPICAL CIRCUIT DIAGRAM 3 13 Rev 1 0 www DataSheet4U com ...

Page 40: ...inimize its PC boards mounting space in addition to its selectable bidirectional driver output sequence and as many as 100 LCD output segments of high pressure resistance and low output impedance it is possible to obtain the highest driver working efficiency for the 1 200 duty panel 2 FEATURES Number of LCD drive output segments 100 Super slim chip configuration Common output ON resistance 750Ω Ty...

Page 41: ...01 Series 3 2 EPSON Rev 1 0 O 0 O99 V0 V1 LCD driver 100 bit Level shifter 100 bit Bidirectional shift register 50 2 bit V4 V5 FR DI3 DIO2 DIO1 YSCL SHL DSPOFF SEL VSS VDD 3 BLOCK DIAGRAM www DataSheet4U com ...

Page 42: ... register operating mode HIGH 50 2 DI3 input LOW 100 Serial data shift clock input The scanning data is shifted at the falling edge Shift direction selection and DIO pin I O control input When SEL HIGH the DI3 input is set to O50 SHL LOW or O49 SHL HIGH When SEL LOW the D13 input is ignored and the DIO inputs are shifted continuously LCD display blanking control input When LOW is input the content...

Page 43: ...m 130µm 144µm Min Min Min Chip edge Chip edge Pad a Opening X Y 110 110µm PAD No 30 to 109 Pad b Opening X Y 110 110µm PAD No 20 to 29 110 to 119 Pad c Opening X Y 110 110µm PAD No 1 to 19 5 PAD Á Pad layout Chip size 13 43 mm 1 76 mm Chip thickness 400 µm Typ AL pad specifications S1D16501D00A www DataSheet4U com ...

Page 44: ...847 52 O32 2693 53 O33 2539 54 O34 2385 55 O35 2232 56 O36 2078 57 O37 1924 58 O38 1770 59 O39 1616 60 O40 1462 61 O41 1308 62 O42 1154 63 O43 1000 64 O44 846 65 O45 693 66 O46 539 67 O47 385 68 O48 231 69 O49 77 70 O50 77 71 O51 231 72 O52 385 73 O53 539 74 O54 693 75 O55 846 76 O55 1000 77 O57 1154 78 O58 1308 79 O59 1462 80 O60 1616 81 O61 1770 82 O62 1924 83 O63 2078 84 O64 2232 PAD Actual dim...

Page 45: ...elect 50 2 bits or 100 bits according to the status of SEL When the 50 2 bits configuration is selected the input of the 50 bit shift register becomes D13 Level shifter This is a level interface circuit used to convert the signal voltage level from the logic system level to LCD drive level LCD driver This driver outputs the LCD drive voltage The relationship among the display blanking signal DSPOF...

Page 46: ...ON 3 7 DIO1 DI3 YSCL SHL LOW 1 200 Duty FR 1 frame Shift register 200 lines DIO2 O0 O1 O2 Q0 V0 V1 V4 V5 V0 V1 V4 V5 V0 V1 V4 V5 Q1 Q2 DSPOFF 100 lines 50 lines when D13 is input where SEL HIGH 7 TIMING CHART www DataSheet4U com ...

Page 47: ...emperature 1 Tstg 1 65 to 150 C VDD 0V System side V V V V V V V V CC DD SS 5 4 1 GND 5V DD 5V 28V 0 8 ABSOLUTE MAXIMUM RATINGS Notes 1 The voltage of V0 V1 V4 and V5 must always satisfy the condition of VDD V0 V1 V4 V5 2 Floating of the logic system power during while the LCD drive system power is applied or exceeding VSS 2 6 V or less can cause permanent damage to the LSI Functional operation un...

Page 48: ...4 2 0 5 0 25 1 0 15 10 15 8 15 Unit V V V V V V V V V V µA µA µA kΩ µA µA pF pF Applicable pin VSS V5 V5 V0 V1 V4 DIO1 DIO2 FR YSCL SHL DI3 DSPOFF SEL DIO1 DIO2 YSCL SHL DI3 DSPOFF FR SEL DIO1 DIO2 VDD O0 O99 VSS V5 YSCL SHL DSPOFF FR DI3 SEL DIO1 DIO2 Parameter Supply voltage 1 Recommended operating voltage Operation enable voltage Supply voltage 2 Supply voltage 3 Supply voltage 4 HIGH input vol...

Page 49: ...YSCL LOW pulsewidth tWCLL 330 ns Data setup time tDS 100 ns Data hold time tDH 10 ns Allowable FR delay time tDFR 300 300 ns VSS 5 0V 0 5V Ta 40 to 85 C Parameter Symbol Condition Min Max Unit Input signal rise time tr 50 ns Input signal fall time tf 50 ns YSCL period tCCL 1000 ns YSCL HIGH pulsewidth tWCLH 160 ns YSCL LOW pulsewidth tWCLL 330 ns Data setup time tDS 200 ns Data hold time tDH 10 ns...

Page 50: ...elay time tpdCFR CL 100pF 1 0 µs VSS 4 5 2 7V Ta 40 to 85 C Parament Symbol Condition Min Max Unit YSCL fall to DIO delay time tpdDOCL CL 15pF 400 ns YSCL fall to On output delay time tpdCCL V5 12 0 to DSPOFF to On output delay time tpdCDOFF 28 0V 2 0 µs FR to On Output delay time tpdCFR CL 100pF 2 0 µs FR On YSCL VIH 0 2 VSS VIL 0 8 VSS VOH 0 2 VSS VOL 0 8 VSS Vn 0 5 Vn 0 5 DSPOFF DIO1 DIO2 tpdDO...

Page 51: ...his causing the LSI to be broken down in some cases When a protection resistor is inserted it is necessary to stabilize the voltage by capacitance Note in power ON OFF Since this LSI is high in the voltage of LCD driving system when a high voltage is applied to the LCD driving system with the logic system power supply kept floating or above VSS 2 5 V an overcurrent flows and LSI breaks down in som...

Page 52: ... to 3 DI01 DI02 DI01 DI02 DI3 HorL S1D16501 S1D16501 80 80 S1D16408 S1D16408 S1D16408 EI01 V DD EI02 EI01 EI02 EI01 8 2 1 EI02 640 200 DOT 1 200 DUTY r r R r r V0 V1 V2 V3 V4 V5 V5 VSS VDD 100 100 11 TYPICAL CIRCUIT DIAGRAM Configuration Drawing of Large Screen LCD www DataSheet4U com ...

Page 53: ...S1D16700 Rev 1 1 www DataSheet4U com ...

Page 54: ...LOCK DIAGRAM 4 2 4 PIN DESCRIPTION 4 3 5 PAD 4 4 6 FUNCTIONAL DESCRIPTION 4 6 7 TIMING CHART S1D16700D01B 4 7 8 ABSOLUTE MAXIMUM RATINGS 4 8 9 ELECTRICAL CHARACTERISTICS 4 9 10 LCD DRIVE POWER 4 12 11 CONNECT EXAMPLE 4 13 Rev 1 1 www DataSheet4U com ...

Page 55: ...tance and low output impedance it is possible to obtain the highest driver working efficiency for the 1 200 duty panel And the S1D16700 01 can display 65 x 132 panel when used as a common driver of RAM buit in driver S1D15301 2 FEATURES Number of LCD drive output segments 100 Common output ON resistance 700 Ω Typ Display duty ratio 1 64 to 1 300 Reference Display capacity Possible to display 640 4...

Page 56: ... COM0 COM99 V1 V4 LCD driver 100 bit shift register 100 bit shift register 100 bit V0 V5 FR DIO1 DIO2 YSCL INH in S1D16700 00 DOFF in S1D16700 01 SHL DOFF INH COM1COM2 VDD VSS Voltage control circuit 3 BLOCK DIAGRAM www DataSheet4U com ...

Page 57: ...n I O control input LCD display blanking control input When LOW is input the content of shift register is cleared and all common outputs become the V0 level instantaneously S1D16700D01B LCD drive display blanking control input When LOW is input the content of shift register is cleared and all common outputs become the non select level instantaneously Common output V4 when FR LOW Common output V1 w...

Page 58: ... 03mm Chip thickness 525µm Au bump die from 400µm Al Pad die from 1 Au bump specification reference values Bump specific High Quarity Au bump Bump size 90µm 90µm Bump height 17µm 28µm 2 AL Pad specification reference values Pad Opening 100µm 100µm 5 PAD Á Pad layout www DataSheet4U com ...

Page 59: ... 56 60 2584 1231 57 61 2298 1357 58 62 2168 59 63 2039 60 64 1910 61 65 1781 62 66 1652 63 67 1522 64 68 1393 65 69 1264 66 70 1135 67 71 1006 68 72 876 69 73 747 70 74 618 71 75 489 72 76 360 73 77 230 74 78 101 75 79 28 76 80 157 77 81 286 78 82 416 79 83 545 80 84 674 1357 PAD Actual dimensions NO NAME X Y 1 COM5 2187 1357 2 6 2058 3 7 1929 4 8 1799 5 9 1670 6 10 1541 7 11 1412 8 12 1283 9 13 1...

Page 60: ...register This is a bidirectional shift register to transfer common data Level shifter This is a level interface circuit used to convert the signal voltage level from the logic system level to LCD drive level LCD driver circuit This driver outputs the LCD drive voltage The relationship among the display blanking signal DOFF contents of shift register AC converted signal FR and common output voltage...

Page 61: ... FR 1 frame Shift register 200 lines DIO2 O0 O1 O2 Q0 V0 V1 V4 V5 V0 V1 V4 V5 V0 V1 V4 V5 Q1 Q2 DSPOFF 100 lines The V1 or V4 non select level is output corresponding to the FR in S1D16700D00B or INH LOW respectively 7 TIMING CHART S1D16700D01B www DataSheet4U com ...

Page 62: ...erature Topr 40 to 85 C Storing temperature 1 Tstg 65 to 150 C VDD 0V 8 ABSOLUTE MAXIMUM RATINGS Notes 1 The voltage of V0 V1 and V4 must always satisfy the condition of VDD V0 V1 V4 V5 2 Floating of the logic system power during while the LCD drive system power is applied or exceeding VSS 2 6 V or more can cause permanent damage to the LSI Functional operation under these conditions is not implie...

Page 63: ...S 0 VSS 0 4 2 0 5 0 25 1 40 15 10 15 8 15 Unit V V V V V V V V V V V V µA µA µA kΩ µA µA pF pF Parameter Supply voltage 1 Recommended operating voltage Operation enable voltage Supply voltage 2 Supply voltage 3 Supply voltage 4 HIGH input voltage 1 LOW input voltage 1 HIGH input voltage 2 LOW input voltage 2 HIGH output voltage LOW output voltage Input leakage current Input output leakage current ...

Page 64: ...ld time tDH 10 ns Allowable FR delay time tDFR 500 500 ns Unless otherwise specified VSS 2 7V to 4 5V Ta 40 to 85 C Parameter Symbol Condition Min Max Unit Input signal rise time tr 50 ns Input signal fall time tf 50 ns YSCL period tCCL 1000 ns YSCL HIGH pulsewidth tWCLH 160 ns YSCL LOW pulsewidth tWCLL 330 ns Data setup time tDS 200 ns Data hold time tDH 10 ns Allowable FR delay time tDFR 500 500...

Page 65: ... otherwise specified VSS 2 7V to 4 5V Ta 40 to 85 C Parament Symbol Condition Min Max Unit YSCL fall to DIO delay time tpdDOCL CL 15pF 60 600 ns YSCL fall to COM output delay time tpdCCL V5 7 0 to DOFF to COM output delay time tpdCDOFF 28 0V 3 0 µs INH to COM output delay time tpdCINH CL 100pF FR to COM output delay time tpdCFR 3 0 µs FR Vn 0 5V Vn 0 5V tpdDOCL tpdCCL tpdCFR tpdCDOFF YSCL VIH 0 2 ...

Page 66: ...er is employed the maximum potential level V0 for LCD driving has been isolated from the VDD pin When the potential of V0 lowers than that of VDD and the potential difference between the two becomes larger however the capacity of LCD drive output driver lowers To avoid it use the system with the potential difference of 0 V to 2 5 V between V0 and VDD When no operational amplifier is used connect V...

Page 67: ...IO1 DIO2 FR FR S1D16700D LP YD V SS V DD V 0 V 1 V 2 V 3 V 4 V 5 VSSH WF XSCL XD0 XD3 V SS 6 6 R R R R 11R 322Ω 322Ω FR LP D0 3 XSCL FR LP D0 3 XSCL FR LP D0 3 XSCL S1D16006D COM 0 99 COM 0 99 Note 1 It must be provided as the protective resister against overcurrent Also the bypass capacitor 0 01 µF for noise suppression must be provided near to VSS and V5 terminals on each LSI www DataSheet4U com...

Page 68: ...S1D16702 Rev 1 0 www DataSheet4U com ...

Page 69: ...2 4 PIN DESCRIPTION 5 3 5 PIN LAYOUT 5 4 6 PAD 5 5 7 FUNCTIONAL DESCRIPTION 5 6 8 TIMING CHART 5 7 9 ABSOLUTE MAXIMUM RATINGS 5 8 10 ELECTRICAL CHARACTERISTICS 5 9 11 LCD DRIVE POWER 5 13 12 DIFFERENT POINTS FROM REPLACEMENT PRODUCT 5 14 Rev 1 0 www DataSheet4U com ...

Page 70: ...equence It also has 68 LCD output segments of high pressure resistance and low output impedance It can display the 65 132 panel when used as the expansion driver of S1D15301 being built in RAM S1D16702 01 2 FEATURES Number of LCD drive output segments 68 Common output ON resistance 700 Ω Typ Display duty ratio 1 64 to 1 300 Reference Display capacity Possible to display 640 480 dots when used in c...

Page 71: ...EPSON Rev 1 0 COM0 COM67 V1 V4 LCD driver 68 bit shift register 68 bit shift register 68 bit V0 V5 FR DIO1 DIO2 YSCL SHL INH COM1COM2 VDD VSS DOFF INH in S1D16702 00 DOFF in S1D16702 01 3 BLOCK DIAGRAM www DataSheet4U com ...

Page 72: ...ing edge Display data latch pulse input Falling edge trigger Shift direction selection and DIO pin I O control input LCD display blanking control input when LOW is input the content of shift register is cleared and all common outputs become the non select level instantaneously S1D16702 01 LCD display blanking control input When LOW is input the content of shift register is cleared and all common o...

Page 73: ...COM 32 31 COM 33 32 COM 34 33 COM 35 34 COM 36 35 COM 37 36 COM 38 37 COM 39 38 COM 40 39 COM 41 40 COM 42 41 COM 43 42 COM 44 43 COM 45 44 COM 46 45 COM 47 46 COM 48 47 COM 49 48 COM 50 49 COM 51 50 COM 52 51 COM 53 52 COM 54 53 COM 55 54 COM 56 55 COM 57 56 COM 58 57 COM 59 58 COM 60 59 COM 61 60 COM 62 61 COM 63 62 COM 64 63 COM 65 64 COM 66 65 COM 67 66 DIO2 67 INH 68 FR 69 YSCL 70 SHL 71 VDD ...

Page 74: ...76 21 COM 22 1005 22 COM 23 1135 23 COM 24 1264 24 COM 25 1393 25 COM 26 1522 26 DM 1651 27 DM 1781 1357 28 DM 1976 1098 29 COM 27 1976 969 30 COM 28 1976 840 31 COM 29 1976 711 32 COM 30 581 33 COM 31 452 34 COM 32 323 35 COM 33 194 36 COM 34 65 37 COM 35 65 38 COM 36 194 39 COM 37 323 40 COM 38 452 41 COM 39 581 42 COM 40 711 43 COM 41 840 44 COM 42 969 45 DM 1976 1098 46 DM 1743 1357 47 DM 1614...

Page 75: ...ION Shift register This is a bidirectional shift register to transfer common data Level shifter This is a level interface circuit used to convert the signal voltage level from the logic system level to LCD drive level LCD driver circuit This driver outputs the LCD drive voltage The relationship among the display blanking signal INH contents of shift register AC converted signal FR and common outpu...

Page 76: ...D16702 Series Rev 1 0 EPSON 5 7 DIO1 YSCL SHL LOW 1 200 Duty FR 1 frame Shift register 200 lines DIO2 O0 O1 O2 Q0 V0 V1 V4 V5 V0 V1 V4 V5 V0 V1 V4 V5 Q1 Q2 INH 68 lines 8 TIMING CHART www DataSheet4U com ...

Page 77: ...ature Tstg 65 to 150 C Soldering temperature and time Tsol 260 C 10sec 9 ABSOLUTE MAXIMUM RATINGS Notes 1 The voltage of V0 V1 and V4 must always satisfy the condition of VDD V0 V1 V4 V5 2 Floating of the logic system power during while the LCD drive system power is applied or exceeding VSS 2 6 V or more can cause permanent damage to the LSI Functional operation under these conditions is not impli...

Page 78: ... V V V V V V V µA µA µA kΩ µA µA pF pF Parameter Supply voltage 1 Recommended operating voltage Operation enable voltage Supply voltage 2 Supply voltage 3 Supply voltage 4 HIGH input voltage 1 LOW input voltage 1 HIGH input voltage 2 LOW input voltage 2 HIGH output voltage LOW output voltage Input leakage current Input output leakage current Static current Output resistance Average operating curre...

Page 79: ...EPSON Rev 1 0 2 0 2 4 3 0 4 0 5 0 5 5 6 VSS V 30 28 20 10 7 0 0 V 5 V Operating Voltage Range Operating Voltage Range VSS V5 V5 voltage must be set within the following operating voltage range of VSS V5 www DataSheet4U com ...

Page 80: ... time tDH 10 ns Allowable FR delay time tDFR 500 500 ns Unless otherwise specified VSS 2 7V to 4 5V Ta 40 to 85 C Parameter Symbol Condition Min Max Unit Input signal rise time tr 50 ns Input signal fall time tf 50 ns YSCL period tCCL 1000 ns YSCL HIGH pulsewidth tWCLH 160 ns YSCL LOW pulsewidth tWCLL 330 ns Data setup time tDS 200 ns Data hold time tDH 10 ns Allowable FR delay time tDFR 500 500 n...

Page 81: ...s otherwise specified VSS 2 7V to 4 5V Ta 40 to 85 C Parament Symbol Condition Min Max Unit YSCL fall to DIO delay time tpdDOCL CL 15pF 60 600 ns YSCL fall to COM output delay time tpdCCL V5 7 0 to 3 0 µs INH to COM output delay time tpdCINH 28 0V FR to COM output delay time tpdCFR CL 100pF 3 0 µs FR Vn 0 5V Vn 0 5V tpdDOCL tpdCCL tpdCFR tpdCINH YSCL VIH 0 2 VSS VIL 0 8 VSS INH COM DIO1 DIO2 The s...

Page 82: ...m ON or simultaneous ON of the both At power OFF LCD driving system OFF Logic system OFF or simultaneous OFF of the both Precautions Users of this development specification are reminded of the following precautions 1 This development specification is subject to change without previous notice 2 This specificatino does not warrant the user to exercise the industrial property right or other rights no...

Page 83: ...l shift register INH INH 68 output segments 68 output segments Output Tr configuration Fig 1 Fig 2 PAD layout Identical to the equivalent product PAD coordinates Different from the equivalent product COM V0 V1 V4 V5 COM V0 V5 V1 V4 FIg 2 Fig 1 12 DIFFERENT POINTS FROM REPLACEMENT PRODUCT www DataSheet4U com ...

Page 84: ... E 08190 Sant Cugat del Vallès SPAIN Phone 34 93 544 2490 Fax 34 93 544 2491 ASIA EPSON CHINA CO LTD 28F Beijing Silver Tower 2 North RD DongSanHuan ChaoYang District Beijing CHINA Phone 64106655 Fax 64107319 SHANGHAI BRANCH 4F Bldg 27 No 69 Gui Jing Road Caohejing Shanghai CHINA Phone 21 6485 5552 Fax 21 6485 0775 EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Phone 852...

Page 85: ...or circuit and further there is no repersesnation that this material is applicable to products requiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of...

Page 86: ...D16000 Series EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION First issue November 1990 Printed May 2001 in Japan H A 4 5mm This manual was made with recycle paper and printed using soy based inks Technical Manual LCD DRIVERS S1D16000 Series http www epson co jp device www DataSheet4U com ...

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