Epson S1D16000 Series, Technical Manual

Page: 15 / 86

S1D16006 Series
Rev.2.1
EPSON
1–7
7. FUNCTIONAL DESCRIPTION
Enable shift register
This is a bidirectional shift register with which the shift direction is selected by SHL input. The output of this
shift register is used to store the data bus signals to data register.
When the enable signal is in the disable status, the internal clock signal and data bus are fixed to LOW and
the system is made into the power save mode.
When using two or more segment drivers, connect the EIO pin of each driver in a cascade arrangement and
the EIO pin of the leading driver to V
DD
.
Since the enable controller circuit automatically detects that the data for 80 bits have been fetched thoroughly
and then transfers the enable signal to the controller, it is not necessary to provide the control signal using the
control LSI.
Data register
This is a register used to convert the data bus signal into serial or parallel signal through the enable shift register
output. Consequently, the relationship between the serial display data and segment output is determined
irrespective of the number of shift clock inputs.
Latch
This latch is used to fetch the content of data register at the LP falling edge trigger and to send its output to
the level shifter.
Level shifter
This is a level interface circuit used to convert the signal voltage level from the logic system level to LCD drive
level.
LCD driver
This driver outputs the LCD drive voltage.
The relationship among the data bus signal, AC converted signal FR and segment output voltage is as shown
in the table below:
Data bus
FR O output voltage
signal
HIGH V
0
HIGH
LOW V
5
HIGH V
2
LOW
LOW V
3
(S1D16006D00
**
)
(S1D16006D01
**
)
DSPOFF
Data bus
FR O output voltage
signal
HIGH HIGH
HIGH V
0
LOW V
5
HIGH LOW
HIGH V
2
LOW V
3
LOW — — V
0
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