Epson S1D16000 Series, Technical Manual

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S1D16006 Series
Rev.2.1
EPSON
1–3
Function
Segment (column) output for LCD driving
The output changes at the LP falling edge.
Display data input
Display data shift clock input (Falling edge trigger)
Display data latch pulse input (Falling edge trigger)
Enable input/output
To be set to input or output according to the SHL input level.
The output is reset by the LP input. Upon the end of fetching of
80-bit data, the system starts up automatically to HIGH.
Shift direction selection and EIO pin I/O control input When data
is input to (D3, D2 ... D0 ) pins sequentially in order of (a3, a2,
a1, a0), (b3, b2, b1, b0) ... (t3, t2, t1, t0), the relationship
between the data and segment output becomes as shown in the
table below:
(Note) The relationship between the data and segment output is
determined irrespective of the number of shift clock
inputs.
LCD drive output AC converted signal input
Force input of blank
V0 level is forcibly set by entering LOW level (available with
S1D16006D01
** alone).
Logic power supply V
DD
: 0 V V
SS
: –2.7 V to –5.5 V
LCD drive circuit power supply
V
DD
: 0 V V
5
: –8 V to –28 V
V
DD
≥
V
0
≥
V
2
≥
6/9 V
5
3/9 V
5
≥
V
3
≥
V
5
When used at a same potential, V
0
and V
DD
are used by
grounding them close to the IC chip.
Number
of pins
Pin name
O0 ~ O79
D0 ~ D3
XSCL
LP
EIO1, EIO2
SHL
FR
DSPOFF
V
DD
, V
SS
V0, V2,
V3, V5
*1
80
4
1
1
2
1
1
1
2
4
O Output EIO
SHL
79 78 77 2 1 0 EIO1 EIO2
LOW a3 b2 c1 . . . t2 t1 t0 Output Input
HIGH t0 t1 t2 . . . a1 a2 a3 Input Output
I/O
O
I
I
I
I/O
I
I
I
Power supply
Power supply
*1 Be sure to connect V
0
to V
5
to their LCD power, respectively. Total: 100
S1D16006D00
**
(including four NC’4)
S1D16006D01
**
(including four NC’3)
4. PIN DESCRIPTION
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