RA8804 CE
Page - 14
ETM60E-02
4) AIE (Alarm Interrupt Enable) bit
When an alarm timer interrupt event occurs (when the AF bit value changes from
“0” to “1”), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status
remains Hi-Z).
When a
“1”
is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a
“0”
is written to this bit, no interrupt signal is generated when an interrupt event occurs.
AIE
Data
Function
Write/Read
0
When an alarm interrupt event occurs, an interrupt signal is not generated or is
canceled (/INT status changes from low to Hi-Z).
1
When an alarm interrupt event occurs, an interrupt signal is generated
(/INT status changes from Hi-Z to low).
When an alarm interrupt event has been generated low-level output from the /INT pin occurs only
when the value of the control register's AIE bit is
“1””. This setting is retained until the AF bit value
is cleared to zero. (No automatic cancellation)
For details, see
“8.7. Alarm Interrupt Function”.
[Caution]
(1) The /INT pin is a shared interrupt output pin for three types of interrupts. It outputs the OR'ed result of these interrupt outputs.
When an interrupt has occurred (when the /INT pin is at low level), the UF,
TF,
read AF flags to determine which flag has a value
of 1
”
(this indicates which type of interrupt event has occurred).
(2) The status of update interrupt, timer interrupt and alarm interrupt can be checked by software polling without using the /INT pin.
In this case, write
“0” into UIE,
TIE,
and AIE bits to avoid physical interrupt generation and thus reduce power consumption.
5) RESET bit
When highly precise synchronization of both time or timer is necessary, use RESET.
RESET
Data
Function
Write/Read
0
The read value of RESET is 0, always.
writes 0, it is invalid.
1
writes 1, it executes reset of count-down-chain from 32.768kHz.
The detailed function of RESET.
For example.
S is start condition. P is stop condition.
[ Write access to RESET-bit.]
S---Slave address(w)---ACK1---0Fh---ACK2---01h---ACK3---P.
RESET executes and it keeps between P from ACK3.
After P, RESET-bit clears automatically.
reset area of circuit are the count-down-chain of 2 Hz from 16 kHz, are cleared.
As for next update timing of a Seconds counter from RESET.
That range is 1000 ms-30.5
s from just 1000 ms.
RESET affects time update interruption, alarm, FOUT and timer.
but, it doesn't affect 32 kHz output.
Note:
RESET is released by the reception of a START or RE-START condition before receiving an STOP condition.
The Single write access is recommended for precise RESET.
Unnecessary use of RESET, will be the cause of delay error of time.
