RA8804 CE
Page - 17
ETM60E-02
2) TSTP (Timer STOP) bit
This bit controls the temporarily stopped of Timer Counter.
TSTP
Data
Description
Write/Read
0
Timer Counter are stopped. (don
’
t reset.)
1
Count down of the Timer Counter are continued.
3)
TRES (Timer Reset) bit
This bit can be employed like Watch Dog Timer function.
TRES
Data
Description
Write/Read
0
The Timer Counter is not affected.
1
Preset value are loaded to all Timer Counters.
4) TE (Timer Enable) bit
This bit controls the start/stop setting for the fixed-cycle timer interrupt function.
TE
Data
Description
Write/Read
0
Preset value loaded to all Timer counter, and count-down stops.
1
Starts fixed-cycle timer countdown.
The countdown that starts when the TE bit value changes from 0
to 1 always begins from the preset
value.
5) TF (Timer Flag) bit
If set to 0 beforehand, this flag bit's value changes from
“0” to “1” when a fixed-cycle timer interrupt event has
occurred. Once this flag bit's value is
“1”, its value is retained until a “0” is written to it.
TF
Data
Description
Write
0
The TF bit is cleared to zero to prepare for the next status detection
Clearing this bit to zero does not enable the /INT low output status to be cleared (to Hi-Z).
1
Invalid (writing a 1 will be ignored)!
Read
0
Fixed-cycle timer interrupt events are not detected.
1
Fixed-cycle timer interrupt events are detected.
(Result is retained until this bit is cleared to zero.)
6) TIE (Timer Interrupt Enable) bit
When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from
“0” to “1”), this bit's value
specifies whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT
status remains Hi-Z).
TIE
Data
Description
Write/Read
0
1) When a fixed-cycle timer interrupt event occurs, an interrupt signal is not
generated or is canceled (/INT status remains Hi-Z).
2) When a fixed-cycle timer interrupt event occurs, the interrupt signal is
canceled (/INT status changes from low to Hi-Z).
Even when the TIE bit value is “0” another interrupt event may change the /INT status to low (or may
hold /INT =
L).
1
When a fixed-cycle timer interrupt event occurs, an interrupt signal is generated
(/INT status changes from Hi-Z to low).
When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin
occurs only when the value of the control register's TIE bit is 1. Earliest 7.813 ms the interrupt occurs,
the /INT status is automatically cleared (/INT status changes from low to Hi-Z).