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RA8804 CE

Page - 34

ETM60E-02

8.10.6. I

2

C bus protocol

In the following sequence descriptions, it is assumed that the CPU is the master and the RA8804 is the slave.

a. Address specification write sequence

Since the RA8804 includes an address auto increment function, once the initial address has been specified, the
RA8804 increments (by one byte) the receive address each time data is transferred.

(1) CPU transfers start condition [S].
(2) CPU transmits the RA8804's slave address with the R/W bit set to write mode.
(3) Check for ACK signal from RA8804.
(4) CPU transmits write address to RA8804.
(5) Check for ACK signal from RA8804.
(6) CPU transfers write data to the address specified at (4) above.
(7) Check for ACK signal from RA8804.
(8) Repeat (6) and (7) if necessary. Addresses are automatically incremented.
(9) CPU transfers stop condition [P].

S

(1)

0

R/W

0

(3)

Address

(4)

0

(5)

0

Data

(8)

P

(9)

ACK signal from RX8900

Data

(6)

0

(7)

(2)

Slave address

b. Address specification read sequence

After using write mode to write the address to be read, set read mode to read the actual data.

(1) CPU transfers start condition [S].
(2) CPU transmits the RA8804's slave address with the R/W bit set to write mode.
(3) Check for ACK signal from RA8804.
(4) CPU transfers address for reading from RA8804.
(5) Check for ACK signal from RA8804.
(6) CPU transfers RESTART condition [Sr] (in which case, CPU does not transfer a STOP condition
[P]).
(7) CPU transfers RA8804's slave address with the R/W bit set to read mode.
(8) Check for ACK signal from RA8804 (from this point on, the CPU is the receiver and the RA8804
is the transmitter).
(9) Data from address specified at (4) above is output by the RA8804.
(10) CPU transfers ACK signal to RA8804.
(11) Repeat (9) and (10) if necessary. Read addresses are automatically incremented.
(12) CPU transfers ACK signal for

“1”.

(13) CPU transfers stop condition [P].

S

(1)

0

R/W

0

(3)

Address

(4)

Sr

(6)

0

(5)

1

R/W

0

(8)

Data

(9)

0

(10)

Data

(11)

P

(13)

1

(12)

ACK from RA8900

ACK from CPU

(7)

Slave address

(2)

Slave address

c. Read sequence when address is not specified

Once read mode has been initially set, data can be read immediately. In such cases, the address for each read
operation is the previously accessed a 1.

(1) CPU transfers start condition [S].
(2) CPU transmits the RA8804's slave address with the R/W bit set to read mode.
(3) Check for ACK signal from RA8804 (from this point on, the CPU is the receiver and the RA8804 is
the transmitter).
(4) Data is output from the RA8804 to the address following the end of the previously accessed
address.
(5) CPU transfers ACK signal to RA8804.
(6) Repeat (4) and (5) if necessary. Read addresses are automatically incremented in the RA8804.
(7) CPU transfers ACK signal for

“1”.

(8) CPU transfers stop condition [P].

S

(1)

1

R/W

0

(3)

Data

(4)

0

(5)

1

(7)

Data

(6)

P

(8)

ACK from CPU

ACK from RX8900

(2)

Slave address

d. The address auto increment in Read/Write.

(1) In Basic time and calendar resister.

Address - - - - - - - 08 - 09 - 0A - 0B - 0C - 0D - 0E - 0F - 00 - 01 - 02 - -

(2) In Extension resister

Address - - - - - - - 18 - 19 - 1A - 1B - 1C - 1D - 1E - 1F - 10 - 11 - 12 - -

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Summary of Contents for RA8804 CE

Page 1: ...ETM60E 02 Preliminary Application Manual Real Time Clock Module RA8804 CE ...

Page 2: ...nd any technical information furnished if any for the development and or manufacture of weapon of mass destruction or for other military purposes You are also requested that you would not make the products available to any third party who may use the products for such prohibited purposes These products are intended for general use in electronic equipment When using them in specific applications th...

Page 3: ...n History Rev No Date Page Description ETM60E 01 30 Apr 2018 Release ETM60E 02 27 Jun 2018 14 40 5 RESET bit it explained detailed function of RESET 8 15 Figure of 32 kHz TCXO was updated SCL and SDA connects to GND ...

Page 4: ...gisters for EVIN Interrupt and Time stamp Function 20 8 5 SOUT Interrupt Function 23 8 5 1 Operation example of SOUT function 23 8 5 2 Related registers for SOUT interrupt functions 24 8 6 Time Update Interrupt Function 25 8 6 1 Time update interrupt function diagram 25 8 6 2 Related registers for time update interrupt functions 26 8 7 Alarm Interrupt Function 27 8 7 1 Diagram of alarm interrupt f...

Page 5: ...ions 1 Overview This module is an I2C bus interface compliant real time clock which includes a 32 768 kHz DTCXO In addition to providing a calendar year month date day hour minute second function and a clock counter function this module provides an abundance of other functions including an alarm function fixed cycle timer function time update interrupt function 32 768 kHz output function Time stam...

Page 6: ...ts a 32 768 kHz signal depend on FSEL bit When output is stopped the FOUT pin Hi Z high impedance FOE Input This is an input pin used to control the output mode of the FOUT pin When this pin s level is high the FOUT pin is in output mode When it is low output via the FOUT pin is stopped INT Output This pin is used to output alarm signals timer signals time update signals and other signals This pin...

Page 7: ...D 3 0 V Ta 85 to 105 C VDD 3 0 V 1 9 1 3 4 2 8 0 3 10 6 XB Ta 0 to 50 C VDD 3 0 V Ta 40 to 85 C VDD 3 0 V Ta 85 to 105 C VDD 3 0 V 3 8 4 5 0 5 8 0 3 Frequency voltage characteristics f V Ta 25 C VDD 1 5 V to 5 5 V 1 0 Max 10 6 V FOUT duty cycle Duty 50 VDD 25 C VDD 1 5 V to 5 5 V 50 10 Oscillation start time tSTA Ta 25 C VDD 1 5 V 5 5 V Ta 40 to 85 C VDD 1 6 V to 5 5 V 1 0 Max 3 0 Max s Aging fa T...

Page 8: ...tion 2 IDD10 VDD 3 V 50 95 High level input voltage VIH1 SCL SDA FOE 0 8 VDD 5 5 V VIH2 EVIN 0 8 VDD VDD Low level input voltage VIL SCL SDA FOE EVIN GND 0 3 0 2 VDD High level output voltage VOH1 FOUT SOUT VDD 5 V IOH 1 mA 4 5 5 0 VOH2 VDD 3 V IOH 1 mA 2 2 3 0 VOH3 VDD 3 V IOH 100 µA 2 9 3 0 Low level output voltage VOL1 FOUT SOUT VDD 5 V IOL 1 mA GND GND 0 5 VOL2 VDD 3 V IOL 1 mA GND GND 0 8 VOL...

Page 9: ...d SDA tr 1 0 0 3 µs Fall time for SCL and SDA tf 0 3 0 3 µs Allowable spike time on bus tSP 50 50 ns Timing chart tHD DAT tSU DAT tHD STA tLOW tHIGH 1 fSCL tr tf tSU STA SDA SCL START CONDITION S BIT 7 MSB A7 BIT 6 A6 ACK A Protocol tBUF tSU STO STOP CONDITION P START CONDITION S P A tHD STA tSU STA S BIT 0 LSB R W S tSP Note 1 As for the communication of I2 C completion of less than 1 second is r...

Page 10: ...L0 UIE TIE AIE RESET 4 0 Writing is avoid Read value is 0 always It can read and write is available avoid Init shows value of after power on Reset Unit is Hex Note After the initial power up from 0 V or in case the VLF bit returns 1 make sure to initialize all registers before using the RTC Be sure to avoid entering incorrect date and time data as clock operations are not guaranteed when the data ...

Page 11: ...128 64 32 16 8 4 2 1 0 0 1D Monitor of Timer1 32768 16384 8192 4096 2048 1024 512 256 0 0 1E Monitor of Timer2 8388608 4194304 2097152 1048576 524288 262144 131072 65536 0 0 1F Timer Counter 2 8388608 4194304 2097152 1048576 524288 262144 131072 65536 0 0 Writing is avoid Read value is 0 always It can read and write is available avoid Init shows value of after power on Reset Unit is Hex 8 1 4 Quic...

Page 12: ...01 02 and up to 59 seconds after which it starts again from 00 seconds When written data to a second register less than a Second counter 512 Hz from 2 Hz is cleared to zero When more highly precise time synchronization is needed RESET bit is most suitable When 60 seconds were written to a second register it returns to 00 second in next update This special update is the same as plus adjustment of l...

Page 13: ...from these bits The auto calendar function updates all dates months and years from January 1 00 to December 31 99 The data format is BCD format For example a date register value of 0011 0001 indicates the 31st Note with caution that writing non existent date data may interfere with normal operation of the calendar counter 2 Date counter Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bi...

Page 14: ...1 bits are also used to set the fixed cycle timer interrupt function When the value in the above fixed cycle timer control register just changes from 01h to 00h the INT pin goes to low level and 1 is set to the TF bit to report that a fixed cycle timer interrupt event has occurred 8 2 5 Extension register Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0D Extension Register TEST W...

Page 15: ...k Write Read 0 0 4096 Hz Once per 244 14 s 0 1 64 Hz Once per 15 625 ms 1 0 Second update Once per second 1 1 Minute update Once per minute 8 2 6 Flag register Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0E Flag register UF TF AF VLF VDET Default 0 0 0 0 0 0 1 1 1 The default value is the value that is read or is set internally after powering up from 0 V 2 o indicates write pr...

Page 16: ...e has been detected so data loss might have occurred and time information might be compromised All registers must be initialized This setting is retained until a is written to this bit 5 VDET Voltage Detection Flag bit This flag bit indicates the status of temperature compensation Its value changes from 0 to 1 when the temperature compensation function has stopped operation due to a supply voltage...

Page 17: ...pt signal is not generated or is canceled INT status changes from low to Hi Z 1 When a time update interrupt event occurs an interrupt signal is generated INT status changes from Hi Z to low When a time update interrupt event occurs low level output from the INT pin occurs only when the value of the control register s UIE bit is 1 This INT status is automatically cleared INT status changes from lo...

Page 18: ...terrupt has occurred when the INT pin is at low level the UF TF read AF flags to determine which flag has a value of 1 this indicates which type of interrupt event has occurred 2 The status of update interrupt timer interrupt and alarm interrupt can be checked by software polling without using the INT pin In this case write 0 into UIE TIE and AIE bits to avoid physical interrupt generation and thu...

Page 19: ...ixed cycle timer starts Fixed cycle timer stops 1 1 2 001 h 000 h 3 4 5 1 6 7 7 7 8 9 1 When a 1 is written to the TE bit the fixed cycle timer countdown starts from the preset value 2 A fixed cycle timer interrupt event starts a countdown based on the countdown period source clock When the count value changes from 01h to 00h an interrupt event occurs After the interrupt event occurs the counter a...

Page 20: ...ixed cycle timer counter 0Bh 0Ch 1Fh these can use as a RAM register In such cases stop the fixed cycle timer function by writing 0 to the TE and TIE bits When writes 00h to all timer counter Timer countdown are stop and new Timer interruption are inhibited 1 TSEL0 1 Timer Select 0 1 bits The combination of these two bits is used to set the countdown period source clock for the fixed cycle timer i...

Page 21: ...does not enable the INT low output status to be cleared to Hi Z 1 Invalid writing a 1 will be ignored Read 0 Fixed cycle timer interrupt events are not detected 1 Fixed cycle timer interrupt events are detected Result is retained until this bit is cleared to zero 6 TIE Timer Interrupt Enable bit When a fixed cycle timer interrupt event occurs when the TF bit value changes from 0 to 1 this bit s va...

Page 22: ...n 820 200 20 ms 12 813 s 820 s 820 min 1229 300 05 ms 19 203 s 1229 s 1229 min 1280 312 50 ms 20 000 s 1280 s 1280 min 1920 468 75 ms 30 000 s 1920 s 1920 min 2048 500 00 ms 32 000 s 2048 s 2048 min 2560 625 00 ms 40 000 s 2560 s 2560 min 3200 0 7813 s 50 000 s 3200 s 3200 min 3840 0 9375 s 60 000 s 3840 s 3840 min 4095 0 9998 s 63 984 s 4095 s 4095 min 16777215 4096 sec 3 days 49 min 4 sec 194 da...

Page 23: ...rs the INT pin output goes low When an EVIN interrupt event occurs INT pin output goes low and this status is then held until it is cleared via the EF bit or EIE bit 5 If the EIE value is changed from 1 to 0 while INT is low the INT status immediately changes from low to Hi Z After the alarm interrupt occurs and before the EF bit value is cleared to zero the INT status can be controlled via the EI...

Page 24: ...ified Disabled repeat detection Enables Pull Up resistor Disabled repeat detection Disable interruption of EVIN detection Debounce is disabled When LOW more than about 1 μ seconds is input into an EVIN terminal after this date at that time is recorded EVIN detection interruption signal is output by an INT terminal 8 4 3 Related registers for EVIN Interrupt and Time stamp Function Address Function ...

Page 25: ...h Low detection select bit EHL Data Function Write Read 0 EVIN pin detects active Low level 1 EVIN pin detects active High level 5 EPU Enable Pull Up register bit EPU enables Pull up resistor of EVIN input terminal EPU Data Function Write Read 0 Pull up resistor is disabled 1 Pull up resistor is enabled 6 RCE Enables repeated Time stamp bit RCE Data Function Write Read 0 After time stamp ECP bit i...

Page 26: ... Hi Z to low When a EVIN interrupt event has been generated low level output from the INT pin occurs only when the value of the control register s EIE bit is 1 8 EVMON EVENT Monitor bit EVMON can read the EVIN input level EVMON Data Function Write Read 0 The input level of EVIN is LOW 1 The input level of EVIN is HIGH 9 ET1bit ET0 bit Setup debounce duration debounce duration ET0 1 ET1 ET0 duratio...

Page 27: ...T outputs active LOW 6 WriteRA8804 0x0E 0x3A Clear VDET 7 WriteRA8804 0x19 0x00 SOUT is disabled Ex 2 SOUT use like a GPO port STEP Command example Write Address Data contents Supplement 8 WriteRA8804 0x19 0x00 SOUT is disabled Not 0x69 SOUT is Hi Z 9 WriteRA8804 0x1A 0x80 SOUT is outputs LOW by direct control A WriteRA8804 0x19 0x69 SOUT is enabled SOUT is LOW B WriteRA8804 0x1A 0XC0 SOUT is outp...

Page 28: ...UT status Write Read 0 0 SOUT is output according to SRV FS0 from FS2 0 1 1 0 SOUT outputs LOW SRV doesn t have effect 1 1 SOUT outputs HIGH SRV doesn t have effect 3 SRV Reverse SOUT bit SRV Data Description Write Read 0 The outputs signal of SOUT is active high 1 The outputs signal phase of SOUT is inverted active Low 4 FS Flag select bits FS0 1 2 FS2 FS1 FS0 Select status flag for outputs to SO...

Page 29: ...cleared to zero Operation in RTC int operation Write operation 1 2 3 4 1 5 6 7 1 A time update interrupt event occurs when the internal clock s value matches either the second update time or the minute update time The USEL bit s specification determines whether it is the second update time or the minute update time that must be matched 2 When a time update interrupt event occurs the UF bit value b...

Page 30: ... from 0 to 1 when a time update interrupt event occurs When this flag bit 1 its value is retained until a 0 is written to it UF Data Description Write 0 The UF bit is cleared to zero to prepare for the next status detection Clearing this bit to zero does not enable the INT low output status to be cleared to Hi Z 1 Invalid writing a 1 will be ignored Read 0 Time update interrupt events are not dete...

Page 31: ...g the alarm will not occur until the counter counts up to the current date time i e an alarm will occur next time not immediately 2 When a time update interrupt event occurs the AF bit values becomes 1 3 When the AF bit 1 its value is retained until it is cleared to zero 4 If AIE 1 when an alarm interrupt occurs the INT pin output goes low When an alarm interrupt event occurs INT pin output goes l...

Page 32: ... ignored 2 Alarm registers Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 08 MIN Alarm AE 40 20 10 8 4 2 1 09 HOUR Alarm AE 20 10 8 4 2 1 0A WEEK Alarm AE 6 5 4 3 2 1 0 DAY Alarm 20 10 8 4 2 1 The minute hour day and date when an alarm interrupt event will occur is set using this register and the WADA bit In the WEEK alarm Day alarm register Reg 0Ah the setting selected via the W...

Page 33: ... low to Hi Z Even when the AIE bit value is 0 another interrupt event may change the INT status to low or may hold INT L 1 When an alarm interrupt event occurs an interrupt signal is generated INT status changes from Hi Z to low When an alarm interrupt event occurs low level output from the INT pin occurs only when the AIE bit value is 1 This value is retained not automatically cleared until the A...

Page 34: ...sures the actual temperature of the module and compensates the oscillation frequency of the crystal oscillator using the stored compensation data This way not only the time information is temperature compensated but as well the FOUT signal even when outputting 32 768 kHz This function works in the supply voltage range VTEM 8 9 2 Related registers for temperature compensation function Address Funct...

Page 35: ...s the slave address in the received data In either case the data is transferred via the SCL line at a rate of one bit per clock pulse The I 2 C BUS is a trademark of NXP Semiconductors 8 10 2 System configuration All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices SCL and SDA are both connected to the VDD line ...

Page 36: ...ly stopped at any time while in progress However this is only when this RTC module is in receiver mode data reception mode SDA released 3 When communicating with this RTC module the series of operations from transmitting the START condition to transmitting the STOP condition should occur within 1 seconds A RESTART condition may be sent between a START condition and STOP condition but even in such ...

Page 37: ...ter releases the SDA line and the receiver sets the SDA line to low acknowledge level SCL from Master SDA from transmitter sending side ACK signal 1 2 8 9 SDA from receiver receiving side Release SDA Low active After transmitting the ACK signal if the Master remains the receiver for transfer of the next byte the SDA is released at the falling edge of the clock corresponding to the 9th bit of data ...

Page 38: ...P 7 CPU transfers RA8804 s slave address with the R W bit set to read mode 8 Check for ACK signal from RA8804 from this point on the CPU is the receiver and the RA8804 is the transmitter 9 Data from address specified at 4 above is output by the RA8804 10 CPU transfers ACK signal to RA8804 11 Repeat 9 and 10 if necessary Read addresses are automatically incremented 12 CPU transfers ACK signal for 1...

Page 39: ...ed If such communication requires 2 seconds Max or longer the I2C bus interface is reset by the internal bus timeout function When bus time out occur SDA turns to Hi Z input mode But readout data of a clock is stable anytime and there isn t contradiction And it does not occur that data of a clock delay even if access time is prolonged tR2 is specifications for an oscillation not to stop Some clock...

Page 40: ...ints 1 Please begin to read VLF bit first 2 If VLF bit returns 1 please initialize all registers Please perform initial setting only tSTA oscillation start time when the built in oscillation is stable 3 Access is prohibited within 30 ms the supply voltage exceeds min VCLK clock supply voltage VDD 1 5 V 4 If VLF bit returns 0 access is possible without waiting time 5 Before the internal crystal osc...

Page 41: ...n be used as a RAM register In such cases be sure to write 0 to the AIE bit Setting the Timer function Set the fixed cycle Timer function When the fixed cycle timer function is not being used the Timer Counter register can be used as a RAM register In such cases stop the fixed cycle timer function by writing 0 to the TE and TIE bits Set TE bit to 0 Set FSEL1 0 bit optionally Setting the Update fun...

Page 42: ...al oscillation starts 0 writing of VLF is approved Start up complete power on Wait Wait time of 30 ms is necessary at least Whether it is a return from the state of the backup is confirmed VLF 1 YES YES NO VLF 0 clear Wait VLF 0 Software reset Initialize NO Please set waiting time depending on load of a system optionally ...

Page 43: ...s within 0 95 seconds RESET 1 Set RESET bit to 1 to prevent timer update in time setting 4 The reading of the clock and calendar Next process Reading of the clock Read clock Please complete access within 0 95 seconds At the time of a communication start the Clock Calendar data are fixed hold the carry operation and it is automatically revised at the time of the communication end The access to a cl...

Page 44: ...r Master VDD SCL SDA t r R C BUS Pull up Registor RA8804 SCL SDA GND VDD I C BUS 2 I2 C Bus VDD SDA SCL SLAVE ADRS 0110 010 R W VDD INT EVIN SOUT FOUT FOE 8 15 When used as a clock source 32 kHz TCXO RA8804 VDD T2 GND 0 1 F FOUT INT SCL SDA FOE VDD 32 768kHz O E SOUT EVIN ...

Page 45: ...ease be careful not to connect or short circuit this pads In addition please avoid short circuit between these metal parts by dew condensation or particle adhesion 9 1 2 Marking layout RA8804CE 1 Pin Mark Logo Production lot A8804 X 123A Type X XA Y XB Frequency Stability Contents displayed indicate the general markings and display but are not the standards for the fonts sizes and positioning 3 2 ...

Page 46: ...n exposition when it was specified N C or open by pin exposition 2 Notes on packaging 1 Soldering heat resistance If the temperature within the package exceeds 260 C the characteristics of the crystal oscillator will be degraded and it may be damaged The reflow conditions within our reflow profile is recommended Therefore always check the mounting temperature and time before mounting this device A...

Page 47: ... 86 21 5423 4677 Shenzhen Branch Room 804 805 8F Tower 2 Ali Center No 3331 Keyuan South Rosd Shenzhen Bay Nanshan District Shenzhen 518054 China Phone 86 755 3299 0588 Fax 86 755 3299 0560 Epson Hong Kong Ltd Unit 715 723 7 F Trade Square 681 Cheung Sha Wan Road Kowloon Hong Kong Phone 86 755 2699 3828 Shenzhen Branch Fax 86 755 2699 3838 Shenzhen Branch www epson com hk Epson Taiwan Technology T...

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