Elan eSL Series User Manual Download Page 163

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Chapter 6

eSL/eSLS Series (+ eSLZ000) User’s Manual

Instruction Set Summary

••••

151

(Continued)

Function

Algebra Assembly

Syntax

Operation

W/C

T N Z V C

D=Rs*Rt(SU)

Rs.S*Rt.U

1/1

- - - - -

D=Rs*[Rt] (SU)

Rs.S*[Rt].U

1/1

- - - - -

D=Rs*[Rt++](SU)

Rs.S*[Rt++].U

1/1

- - - - -

D=Rs*[Rt--](SU)

Rs.S*[Rt--].U

1/1

- - - - -

D=Rs*P[Rt](SU)

Rs.S*P[Rt].U

1/2(1)

- - - - -

D=Rs*P[Rt++](SU)

Rs.S*P[Rt++].U

1/2(1)

- - - - -

D=[Rs++]*P[Rt--](SU)

[Rs++].S*P[Rt--].U

1/2(1)

- - - - -

MUL.SU

D=[Rs++]*P[Rt++](SU)

[Rs++].S*P[Rt++].U

1/2(1)

- - - - -

D=Rs*Rt(US)

Rs.U*Rt.S

1/1

- - - - -

D=Rs*[Rt] (US)

Rs.U*[Rt].S

1/1

- - - - -

D=Rs*[Rt++](US)

Rs.U*[Rt++].S

1/1

- - - - -

D=Rs*[Rt--](US)

Rs.U*[Rt--].S

1/1

- - - - -

D=Rs*P[Rt](US)

Rs.U*P[Rt].S

1/2(1)

- - - - -

D=Rs*P[Rt++](US)

Rs.U*P[Rt++].S

1/2(1)

- - - - -

D=[Rs++]*P[Rt--](US)

[Rs++].U*P[Rt--].S

1/2(1)

- - - - -

MUL.US

D=[Rs++]*P[Rt++](US)

[Rs++].U*P[Rt++].S

1/2(1)

- - - - -

D=Rs*Rt(UU)

Rs.U*Rt.U

1/1

- - - - -

D=Rs*[Rt] (UU)

Rs.U*[Rt].U

1/1

- - - - -

D=Rs*[Rt++](UU)

Rs.U*[Rt++].U

1/1

- - - - -

D=Rs*[Rt--](UU)

Rs.U*[Rt--].U

1/1

- - - - -

D=Rs*P[Rt](UU)

Rs.U*P[Rt].U

1/2(1)

- - - - -

D=Rs*P[Rt++](UU)

Rs.U*P[Rt++].U

1/2(1)

- - - - -

D=[Rs++]*P[Rt--](UU)

[Rs++].U*P[Rt--].U

1/2(1)

- - - - -

MUL.UU

D=[Rs++]*P[Rt++](UU)

[Rs++].U*P[Rt++].U

1/2(1)

- - - - -

DIV.S

D=D/Rs(S)

Signed [R1:R0] / Rs

R0 = Quotient

1/17(16)

- * * * *

DIV.U

D=D/Rs

Unsigned [R1:R0] / Rs

R0 = Quotient

1/17(16)

- * * * *

D=D+Rs*Rt

D+Rs*Rt

1/1

- + + + +

D=D+Rs*[Rt]

D+Rs*[Rt]

1/1

- + + + +

D=D+Rs*[Rt++]

D+Rs*[Rt++]

1/1

- + + + +

D=D+Rs*[Rt--]

D+Rs*[Rt--]

1/1

- + + + +

D=D+Rs*P[Rt]

D+Rs*P[Rt]

1/2(1)

- + + + +

D=D+Rs*P[Rt++]

D+Rs*P[Rt++]

1/2(1)

- + + + +

D=D+[Rs++]*P[Rt--]

D+[Rs++]*P[Rt--]

1/2(1)

- + + + +

MAC

D=D+[Rs++]*P[Rt++]

D+[Rs++]*P[Rt++]

1/2(1)

- + + + +

D=D-Rs*Rt

D-Rs*Rt

1/1

- + + + +

D=D-Rs*[Rt]

D-Rs*[Rt]

1/1

- + + + +

D=D-Rs*[Rt++]

D-Rs*[Rt++]

1/1

- + + + +

D=D-Rs*[Rt--]

D-Rs*[Rt--]

1/1

- + + + +

D=D-Rs*P[Rt]

D-Rs*P[Rt]

1/2(1)

- + + + +

D=D-Rs*P[Rt++]

D-Rs*P[Rt++]

1/2(1)

- + + + +

D=D-[Rs++]*P[Rt--]

D-[Rs++]*P[Rt--]

1/2(1)

- + + + +

MAS

D=D-[Rs++]*P[Rt++]

D-[Rs++]*P[Rt++]

1/2(1)

- + + + +

Using RPT instruction to perform this operation only needs 1 cycle

The division instruction ( 1/17(16) ) needs 17 cycles in integer mode and 16 cycles in

fractional mode.

Summary of Contents for eSL Series

Page 1: ...eSLS Series eSLZ000 16 Bits DSP 16 Bits DSP 16 Bits DSP 16 Bits DSP Sound Processor Sound Processor Sound Processor Sound Processor USER S MANUAL ELAN MICROELECTRONICS CORP December 2009 Doc Version...

Page 2: ...blication is furnished under a license or nondisclosure agreement and may be used or copied only in accordance with the terms of such agreement ELAN Microelectronics products are not intended for use...

Page 3: ...nd eSL ICs Parts List and Properties 6 1 4 2 eSLS ICs Parts List and Properties 8 1 5 Typical Applications 9 1 6 Pin Descriptions 10 1 6 1 Power Supply 10 1 6 2 System Control 11 1 6 3 DAC Output 11 1...

Page 4: ...2 Conditional Branch Instruction 31 2 5 3 Shift and Rotation Instructions 32 2 5 4 Data Transfer Instruction 33 2 5 5 Bit Operation Instruction 34 2 5 6 Control Instructions 35 2 5 7 DSP Instruction...

Page 5: ...1 3 Examples 65 3 2 Real Time Clock RTC 66 3 2 1 Real Time Clock and Interrupt Block Diagram 66 3 2 2 Real Time Clock Control Register 67 3 2 3 RTC Timing 68 3 2 4 Examples 70 3 3 Timer 71 3 3 1 Timer...

Page 6: ...119 3 9 2 Examples 122 3 10 I O Pad Architecture 123 3 10 1 CMOS Pad Cofiguration Diagrams 124 3 11 General Purpose Input Output 128 3 11 1 Features 128 3 11 2 I O Port Register Descriptions 129 3 11...

Page 7: ...les 149 6 2 1 Data Transfer Instructions 149 6 2 2 Arithmetic Operation Instructions 150 6 2 3 Logic Operation Instructions 152 6 2 4 Bit Operation Instructions 153 6 2 5 Program Jump Instructions 154...

Page 8: ...Contents viii Contents eSL eSLS Series eSLZ000 User s Manual...

Page 9: ...ver only in Section 3 8 7 and 3 8 8 Modified the Temperature Range in Section 4 2 Modified the Power supply voltage in Section 4 3 1 Modified the example in Section 3 6 4 and 3 5 5 Modified the IP att...

Page 10: ...WDT example in Section 3 1 3 Modify Definition of TCNT2 and TCNT3 in Appendix A Added Algorithm related section in Section 1 4 2009 04 15 1 7 Modify DROM example code in Section 3 7 4 Modify PC 7 0 pu...

Page 11: ...Contents eSL eSLS Series eSLZ000 User s Manual Contents xi...

Page 12: ......

Page 13: ...sis implemented by software A wide range of compression bit rates and various volume levels are supported eSL Series chips are equipped with real instrument waveform which enable the chips to obtain g...

Page 14: ...ory 2K word data RAM eSL and eSLS only 8K word data RAM eSLZ000 only 32 128 256 512K word data ROM eSL only 128 256 512K word data ROM eSLS only External data ROM up to 32MB eSLZ000 only Peripherals R...

Page 15: ...16 2K 16 Data ROM External Up to 16M 16 32K 16 128K 16 256K 16 512K 16 32K 16 128K 16 256K 16 512K 16 Timer 4 8 bit 4 8 bit 4 8 bit 4 8 bit 4 8 bit 4 8 bit 4 8 bit 4 8 bit 4 8 bit Watch Dog Yes Yes Y...

Page 16: ...16 32K 16 32K 16 32K 16 32K 16 Data RAM 2K 16 2K 16 2K 16 2K 16 2K 16 2K 16 Data ROM 128K 16 256K 16 512K 16 128K 16 256K 16 512K 16 Timer 4 8 bit 4 8 bit 4 8 bit 4 8 bit 4 8 bit 4 8 bit Watch Dog Ye...

Page 17: ...omparison between eSLZ000 eSL and eSLS ICs Product No eSLZ000 eSL eSLS JTAG ICE Yes No No Boot SPI Yes No No Total I O number 48 48 24 PortA PortB0 7 Large Current I O number 8 4 8 4 4 PortA 12 15 Wak...

Page 18: ...d control to adjust playback speed Support pitch control to change voice pitch Support sound source detection function to detect the angle of sound position Support speaker dependent recognition to re...

Page 19: ...K 40K 48K 96K bps 8KHz Sampling Rate Range 6kHz 48KHz Recording Yes Yes Yes Yes Yes Yes Yes Yes No Beat Tracking Yes Yes Yes Yes Yes Yes Yes Yes No Speaker Independent Recognition No No No No Yes Yes...

Page 20: ...UP to 2 channel speech with different channel sample rate or 1 channel speech 8 channel melody Coding Type 0 8K 96K bps 8kHz Sampling Rate Range 6KHz 48KHz Speech Speed Pitch Control Yes The product n...

Page 21: ...Typical Applications Long Duration Speech and Melody Playback Voice Recognition Education Learning Products Recording and Playback Products Intelligent Interactive Talking Toys Caller ID DTMF FSK dec...

Page 22: ...ative power supply for CPU digital peripheral and DRAM VSS_PM P 0V Negative power supply for PROM DROM and POR eSL and eSLS only Negative power supply for PRAM and POR eSLZ000 only VSS_OSC P 0V Negati...

Page 23: ...on is by OSCS pin OSCO O X tal oscillator connecting pin OSCS I RC or X tal selection 0 RC 1 X tal PLLC I PLL loop filter capacitor This pin has an internal pull up 150K resistor refer to Chapter 5 Ap...

Page 24: ...tput function PA 9 TCCP3 I O Timer 3 capture input or compare output GPIO I O General purpose input and output function PA 10 EXINT0 I External interrupt 0 input GPIO I O General purpose input and out...

Page 25: ...function PB 15 8 GPIO I Wake up function with programmable pull up resistor NOTE eSLS ICs cannot access PB 15 8 that are always high 1 6 5 3 Port C Attributes and Definitions eSL and eSLZ000 only Nam...

Page 26: ...PD 5 GPO O General purpose output function pin with high drive current 7 Tg delay PD 6 GPO O General purpose output function pin with high drive current 4 Tg delay PD 7 GPO O General purpose output fu...

Page 27: ...I Boot serial input BTCS O Boot chip select BTSCLK O Boot clock BTSO O Boot serial output System Mode Attributes and Definition Name Type Description SYSMOD 0 O System mode status display LSB SYSMOD...

Page 28: ......

Page 29: ...he central processing units can read write data at the same time Furthermore the I O space has an independent address i e the I O mapped I O The different configurations of each domain are explained i...

Page 30: ...ization Program counter PC is the dedicated counter for program address and is automatically modified by control flow processing The eight general purpose registers can be used as Program ROM or RAM p...

Page 31: ...R Bank Select Register is used for MOV instruction When user use 8 bit MOV instruction they must make sure the BSR is correct User doesn t care the BSR if they use 16 bit MOV instruction L Please see...

Page 32: ...vailable eSL Series addressing modes 2 3 1 Register Direct Addressing The operands are in the register file Example R1 R2 R3 General Purpose Registers R0 R7 Rd Rs Rt OP Figure 2 4 Register Direct Addr...

Page 33: ...werful for bulk operation and for operations that need a lot of memory accesses The purpose of the addressing mode is to keep high MAC data path utilization Example D D R3 P R4 and R1 P R5 ROM RAM Spa...

Page 34: ...instruction Rd or Rs specifies the destination or source register respectively For example R RAM_bank A 16 bit data address is contained in the 16 LSBs of a 2 word instruction Rd or Rs specifies the d...

Page 35: ...gram Addressing Program execution continues at Address PC offset 1 The offset is contained in the instruction word Short conditional branch instructions can only get to locations 256 to 255 from the c...

Page 36: ...ster Example R1 R3 10 NOTE R3 is the only register available that can be used as base register 0 65535 Offset OP 0 4 Rs RAM Space GPR Figure 2 12a Data Indirect with 5 Bit Displacement Addressing Oper...

Page 37: ...following pages R1 R0 ACCUMULATOR D D 1 Register Space regs 2 I O Space regs 0 15 PROGRAM COUNTER PC 0 15 STACK POINTER SP 0 15 R0 R1 R2 R3 R4 R5 R6 R7 GENERAL PURPOSE REGISTER 0 15 LOOP COUNTER LC 0...

Page 38: ...dress of the next instruction to be executed Therefore the PC can address up to 64K instruction words Read only 2 4 3 Stack Pointer SP The Stack Pointer holds the 16 bit address of the last used stack...

Page 39: ...COMPARE instructions Same as SUBTRACT instruction For ROTATION instructions The Carry flag is used as a link between the least significant bit LSB and most significant bit MSB Overflow V Flag V is se...

Page 40: ...d Global Interrupt Enable GIE Flag The Global Interrupt Enable bit must be set to 1 for the interrupts to be enabled If reset all maskable interrupts are disabled The GIE bit is cleared by interrupts...

Page 41: ...2 words It is organized into instruction categories grouped by function as shown in the table below There are only 60 instructions which make software development quite convenient Function Groups Inst...

Page 42: ...6 16 ALU OP 16 Status Register Negate Figure 2 14 The ALU unit Logic and Mathematic Instruction Definitions Mnemonic Description Operand ADD Addition without carry Rn Rn 6imm 16imm ADC Add with Carry...

Page 43: ...le IF EQ JMP Jump if equal If Z 1 then jump to PC n 1 Simple IF PL JMP Jump if plus If N 0 then jump to PC n 1 Simple IF MI JMP Jump if minus If N 1 then jump to PC n 1 Simple IF TC JMP Jump if test T...

Page 44: ...ed out bits are all passed through the C flag bit The Rotation performs rotation operation though register and the C flag bit Use arithmetic shift right ASR for keeping the sign bit Shift and Rotation...

Page 45: ...space while PUSH and POP instructions provide a channel between register and stack or I O and stack There are two kind data memory mov instruction one is 8 bit mov instruction user need to set BSR and...

Page 46: ...PUSH IO 7 Save the content of IO port 7 on the stack POP IO 8 Read stack to IO port 8 PUSH Rs Write Rs register to stack POP Rd Restore Rd from stack 2 5 5 Bit Operation Instruction These Operations...

Page 47: ...Repeat RPT function may be tied in with such instructions as Multiply Accumulate MAC and Block Moves MOV to increase execution speed of RPT instruction These multicycle instructions effectively become...

Page 48: ...ent It can multiplex its output using a scaler controlled by I O instruction to support either fractional or integer results Under the fractional operation the result is shifted one bit to the left Un...

Page 49: ...executed Initial XOR result is 0 2 Shift the register pair R1 R0 one bit to the left Move the inverted result of XOR operation into the LSB 3 Compare the divisor and result sign bit XOR operation NOT...

Page 50: ...B less than the correct result The quotient produced by a division is only 16 bits in R0 Input operands must be of the same type signed or unsigned and produce a result of the same type In division th...

Page 51: ...ripherals DRAM Low current High speed 3V eSL eSLZ000 eSLS IOVDD_PWM IOVSS_PWM GPO Port D High drive Output PWM Driver PortA 0 1 I O pad High current but high noise 3V 5V eSL eSLZ000 eSLS IOVDD_PB IOVS...

Page 52: ...sic frequency F32K as multiplicand see Section 2 7 2 2 to support frequencies used for Timer and Pulse Width Modulation PWM Note that the FSYS also sources its frequency from FPLL The system clock fre...

Page 53: ...2768Hz crystal oscillator The crystal connects between OSCI pin and OSCO pin The OSCI and OSCO pins connect to ground through a 20pF capacitor individually NOTE During Over Drive when OD 1 the 32768 H...

Page 54: ...rom 1MHz to 32MHz FPLL FSR F32k The PLL Output Frequency Selections FSR Bit DIR Description Reset Value FSR 9 0 R W FPLL Frequency MHz selection 0x000 0x01F Not Available 0x020 0x020 F32k 0x021 0x021...

Page 55: ...get Refer to the library guide see eSL Series C Macro Reference Manual and eSL Series Assembler Reference Manual for further detailed information The folowing shows an example unsigned int pll_value p...

Page 56: ...1 8 divides clock by 8 or FSYS FPLL 8 11 1 1 not divided 00 SMC 2 0 R W System operation mode control 000 FAST mode 001 SLOW mode 01X GREEN mode 1XX SLEEP mode 0x000 Refer to Warm up TimeOut in Figure...

Page 57: ...Address 0x0000 must be a Long JMP instruction to the reset handling routine If the program never enables an interrupt source the interrupt vectors are not used and regular program code can be placed...

Page 58: ...leared When power on reset or RESET pin is at low condition the SMC bits are set to 000 at FAST mode The program counter PC is cleared to all 0 VRST VDD RESET Warm up TimeOut Timer Clear Internal Rese...

Page 59: ...wer on reset voltage Otherwise if the voltage supply is lower than the power on reset voltage a reset will occur VPOR VRST VDD RESET Warm up Time Out Timer Clear Internal Reset Timer Overflow a Power...

Page 60: ...oltage see VBOR in the Figure below the BOR forces the internal RESET to high active To avoid power drop noise due to motor SPK drop test or VDD short period spike noise application of the low voltage...

Page 61: ...tion between the modes is not without restrictions Proper transitions among these modes are illustrated in the figure below 2 9 1 Block Diagram RESET SLOWMode 001 FASTMode 000 GREENMode 01X SLEEPMode...

Page 62: ...well as the oscillator start running ELAN eSL Series are also awaken from GREEN mode by an RTC wake up NOTE For power optimization each peripheral must disable while enter sleep and green mode such a...

Page 63: ...oon as the Reset is cleared by the RESET pin The chip is also reset when the watchdog timer overflows and exception handling starts Exception handling is the same as exception handling by the RESET pi...

Page 64: ...External INT1 EXINTIF1 0x0016 RTC set 0 interrupt flag RTCIF0 0x0018 RTC set 1 interrupt flag RTCIF1 0x001A RTC set 2 interrupt flag RTCIF2 0x001C RTC set 3 interrupt flag RTCIF3 0x001E PWM duty inte...

Page 65: ...on 2 4 5 Status Register SR It must be set to 1 for the interrupts to be enabled If reset all maskable interrupts are disabled The GIE bit is cleared by interrupts and restored by the RETI instruction...

Page 66: ...Enable 0 Disable 0 RTCIE3 11 R W 1 Enable 0 Disable 0 PWMDIE 12 R W 1 Enable 0 Disable 0 PWMPIE 13 R W 1 Enable 0 Disable 0 SPIE 14 R W 1 Enable 0 Disable 0 Except eSLS DROMIE 15 R W 1 Enable 0 Disabl...

Page 67: ...WMPIF 13 R W 1 Interrupt flag is set 0 Clear 0 SPIF 1 14 R W 1 Interrupt flag is set 0 Clear 0 Except eSLS 2 DROMIF 15 R W 1 Interrupt flag is set 0 Clear 0 1 SPIF SPI Transfer Complete Flag This stat...

Page 68: ...0 TOIP2 4 R W 1 High 0 Low 0 TIP3 5 R W 1 High 0 Low 0 TOIP3 6 R W 1 High 0 Low 0 EXINTP1 7 R W 1 High 0 Low 0 RTCIP0 8 R W 1 High 0 Low 0 RTCIP1 9 R W 1 High 0 Low 0 RTCIP2 10 R W 1 High 0 Low 0 RTC...

Page 69: ...sing edge Falling edge Low level Both edge Wakeup 2 11 1 External Interrupt Control Register The External Interrupt Control Register Attributes and Definitions EICON Bit DIR Description Reset Value 1...

Page 70: ...g edge trigger function is shown in a falling edge trigger in b low level interrupt in c and both edge trigger in d Figure 2 26 External Interrupt Function Diagram EXINTIF 0 1 PortA 10 11 Cleared by s...

Page 71: ...ual to Address 0x0000 of RAM In special cases such as in Cases c and d in the following block diagram you will not use the Stack Pointer SP to point to the last address of RAM or SPLIM but rather poin...

Page 72: ...SP SP SP SP dynamic dynamic dynamic dynamic range range range range SP SP SP SP 0x0000 0x0000 0x0000 0x0000 2 2 2 2 Data Data Data Data usable usable usable usable range range range range 0x07FF SP 1...

Page 73: ...0000 of RAM memory The two reasons behind it are first the dynamic operative range of SPA is large enough for the required usage The other is that the SPLIM will restrict the SP from going under Addre...

Page 74: ...ly Furthermore under Case c you may use BS and BC in RAM Address 0x0000 to 0x0007 as its memory management is user definable CAUTION SP value can NOT be equal to SPLIM value in Case c and d Otherwise...

Page 75: ...e 5 bit Basic Timer can only perform as a normal interval timer to request for interrupt service The Watchdog Timer Attributes and Resources Item Resource Clock source F32k Usage register WDTCON Inter...

Page 76: ...eset signal with the WDTEN bit set to 1 at the same time When disabled WDTREN 0 the Watchdog Timer functions only as timing interval to obtain WDT Interrupt Flag WDTIF value Watchdog Timer Control WDT...

Page 77: ...ample B Set watchdog as general 8bit timer no reset and output square waveform to PORTA7 include interruptvector def POWERON R0 0X0080 Set PORTA7 output IO PDIRA R0 R0 0X0002 IO WDTCON R0 Clear WDT ti...

Page 78: ...CON Control register as explained in Section 3 2 2 Real Time Clock Control Register The Real Time Clock Attributes and Resources Item Resource Clock source F32K Usage register RTCCON Interrupt sources...

Page 79: ...er Attributes and Resources RTCCON Bit DIR Description Reset Value RTCEN 15 R W RTC enable disable 0 Disable 1 Enable 0 RTCWKUP3 11 R W 1 RTCS3 enable wakeup 0 disable 0 RTCWKUP2 10 R W 1 RTCS2 enable...

Page 80: ...T a Case T F if F T up Warm RTCX RTCX up Warm period up Wake up Warm RTCX RTCX period up Wake up Warm RTCX RTCX period up Wake Where 1 period Wakeup T _ is the wake up period at different conditions 2...

Page 81: ...y Rising Edge Miss the FallingEdge Figure 3 3b RTC Wake up Timing Diagram in Case b Case c RTC1 01 Mode Timing Diagram RTCS1 01 and WUPS 00 1 2FRTCX 8ms 32 001ms Warm up Process Sleep Miss the Rising...

Page 82: ...Initial SecData R0 0X8003 IO RTCCON R0 enable RTC no wake up RTC0 clock source 1 32k 1HZ BS IO SR GIE Enable GIE BS IO INTE0 RTCIE0 Enable RTC0 interrupt _Delay Main loop JMP _Delay RTC0 interrupt fu...

Page 83: ...as time counter 12 bitPrescaler TCON0 1 ControlLogic Clock Selector Timer0 Timer1 FPLL TIF0 TIF1 Figure 3 4 General Timer Function Block Diagram Timer0 Timer1 Attributes and Resources Item Timer 0 Ti...

Page 84: ...TRL0 7 0 R W Used to store the auto reload value 8 bit of Timer0 0x00 Timer0 Control TCON0 Register Attributes and Definitions TCON0 Bit DIR Description Reset Value TEN0 15 R W Timer Enable this bit e...

Page 85: ...56 100 FPLL 512 101 FPLL 1024 110 FPLL 2048 111 FPLL 4096 000 3 3 1 4 Examples Set Timer0 to count and output a square waveform to PORTA7 include interruptvector def POWERON R0 0x0080 IO PORTA R0 Set...

Page 86: ...imer 2 Timer 3 Clock source FPLL TEXI2 F32k FPLL TEXI3 TVIF2 Usage register TCNT2 TCCR2 TCON2 TCNT3 TCCR3 TCON3 Interrupt sources TIF2 TVIF2 TIF3 TVIF3 I O function pin TEXI2 TCCP2 TEXI3 TCCP3 Operati...

Page 87: ...6 Timer2 3 Function Block Diagram Where Prescaler The prescaler is a 12 stage divider chain providing frequencies based on the CLK input Each set of timers uses the same prescaler as its clock source...

Page 88: ...on pin TCCP Capture can take place at rising edge falling edge or at both edges With the Capture function you can measure the time difference between external events If a valid trigger signal on the p...

Page 89: ...l The TCNT value is stored in TCCR when Input Capture occurs TCNT Value H FF Timer Overflow Interrupt Flag is set Timer Interrupt Flag is set TCCRValue TCCP Input H 7F H 1F H 1F H 7F b TIOM 01 TCNT Va...

Page 90: ...s because the match signal does not clear the counter value and the timer can run up to the overflow of counter value and generates an overflow interrupt at the same time After the counter value overf...

Page 91: ...se of TIOM 10 as shown in the center figure b the TCCP toggles when match condition occurs but the counter value will only reset when overflow occurs In PWM mode PWM waveforms are generated by using T...

Page 92: ...edge on the clock signal internally or externally to start counting The counter is modified at the clock rising edge When the counter starts at arrival of the pertinent selected clock the first count...

Page 93: ...ch TIF2 TVIF2 When TM2 1 Capture 00 Input capture at rising edge of the TCCP pin 01 Input capture at falling edge of the TCCP pin 1X Input capture at rising and falling edges of the TCCP pin 00 TM2 3...

Page 94: ...R W Timer counter clear TCNT 0 Not effect 1 Clear TCNT 0 TIOM3 5 4 R W If TM3 0 Compare 00 No output at compare match TIF3 01 Output toggles to the TCCP pin and reset TCNT at TCCR compare match TIF3 1...

Page 95: ...ividually TIOM2 TIOM3 remain valid for 8 bit counter In order to latch the external input TCCP3_input speed must be under 16kHz when in SLOW mode and under 1 2 system clock when in NORMAL mode 3 3 2 6...

Page 96: ...In particular this PWM module supports audio speaker power and motion control applications 3 4 1 Features 10 bit glitch less Double Buffer PWM output PWM resolution is adjusted by PWM Period Register...

Page 97: ...er as the main latch and PWMD buffer set as the Secondary latch will ensure a glitch less transition function of the PWM You must perform the following steps to configure the output compare module for...

Page 98: ...signals are produced by the module when the PWM time base is configured in an Up Down Counting mode These signals have twice the period of left edge aligned PWM as illustrated at the bottom of the fol...

Page 99: ...11 1111 10 0000 0000 10 0000 0001 10 0000 0010 10 0000 0011 11 1111 1110 11 1111 1111 Single ended PWMP 0x7FC0 PWM 1 PWM 0 PWMD duty ratio 1 2 3 2 1 2 1 3 4 1 00 0000 0000 00 0000 0001 00 0000 0010 00...

Page 100: ...PWMRPT 8 6 R W This field determines the number of PWMD buffer data usage The seven repeats means that each buffer data should be used in the Timer seven times before taking the next data in PWMD 000...

Page 101: ...A0 PWM1 A1 output IO PDIRA R0 R0 0X0200 IO PWMCON R0 Clear and disable PWM counter R0 0X1FC0 IO PWMD R0 Set PWM duty 1 16384000 0X7F 1 7 8us R0 0x7FC0 Set PWM period 1 16384000 0x1FF 1 31 25us IO PWMP...

Page 102: ...efinitions Item Resource Clock source Timer0 1 interrupt Usage register DACD DACCON I O function pin DACO Operation mode Unsigned 2 s complement 3 5 2 Operation DA 11 0 Output Current FFF FFE N 001 00...

Page 103: ...transistor base and emitter to reduce collector current VO VDD Figure 3 13 Using DAC Function to Drive a Speaker Circuit Diagram 3 5 5 Examples Set DAC output data from 0 to 0xFFF0 by adding 0x0010 P...

Page 104: ...ADC and a voltage reference There are 8 single ended analog input channels in the module The XP YP input channel which is integrated with the touch panel shares the common pins with two general analog...

Page 105: ...to 32kHz sampling rate No miss code 11 bits External reference supply VREF Provide VREF internal reference for MIC AGC front end 3 6 2 Registers Start A D conversion is set with ADST bit In Single mod...

Page 106: ...0 Disable 1 Enable 0 SDB 8 R W Single or differential mode selection this bit is active only when TPEN 1 0 Differential reference mode 1 Single ended reference mode 0 ADCLK 7 5 R W Clock Source this...

Page 107: ...o 1 3 6 3 Operation 3 6 3 1 Single Mode Under Single mode A D conversion is performed only once for the analog input on a specified single channel or as follows 1 A D conversion starts from the first...

Page 108: ...ADIF interrupt request is generated 4 The ADST bit is not automatically cleared to 0 Steps 2 and 3 are repeated as long as the ADST bit remains set at 1 When ADST bit is cleared to 0 A D conversion st...

Page 109: ...AD SINGLE 0 3 Set ADC Single mode ch0 clk FPLL 64 ADC_WAIT NOP NOP NOP Wait ADC interrupt BTEST BUF PD 0 Check ADC conver end IF TC JMP ADC WAIT R0 BUF PD ADC trans OK Read data IO PORTA R0 Out read...

Page 110: ...Chapter 3 98 Peripheral Control eSL eSLS Series eSLZ000 User s Manual BC IO INTF1 ADIF RETI...

Page 111: ...esponse code _TouchPad_read TPAD_ON 10 10 TP_RAM R2 R2 OR 0x00 Touch Pad Read end response code IF EQ JMP _TouchPad_Out CMP R2 R7 Touch Pad No Touch response code IF EQ JMP _SLEEP_Mode JMP _TouchPad_r...

Page 112: ...for the detailed ROM size data for each of the eSL Series chips 3 7 1 Features Reading table of data in sequential address Auto increase or auto decrease address after IO DROMD read instruction Data...

Page 113: ...OMD Register Attributes and Definitions DROMD Bit DIR Description Reset Value DROMD 15 0 R Data ROM Data out 0xuuuu 1 1 u unknown value Data ROM Low Address DROMLA Register Attributes and Definitions...

Page 114: ...OMCON first and then set DROMHA finally set DROMLA as illustrated in the Application Examples below 3 7 4 Examples Read 128 word table data from ROM to RAM buffer DATA DataBuffer DS 128 Define RAM dat...

Page 115: ...Chapter 3 eSL eSLS Series eSLZ000 User s Manual Peripheral Control 103...

Page 116: ...ritten to the transmit buffer register Data read back from receive buffer register is right aligned Full duplex Simultaneous receive and transmit operation Clocking 4 programmable clocking schemes Int...

Page 117: ...User s Manual Peripheral Control 105 SPI Attributes and Definitions Item Resource Clock source Fsys Usage register SPICON SPISR SFDR TDBR RDBR Interrupt sources SPIF I O function pin SCK MOSI MISO SS...

Page 118: ...8 3 Pin Description Figure 3 18 SPI System Master Slave Device Block Diagram SPI Pin Attributes and Definitions Pin Type Description SCK I O Serial clock out master mode Serial clock in slave mode MOS...

Page 119: ...ency For exmple the system clock is 16MHz in SPI slave and SPI master The master SPR should be 010 011 100 101 110 111 The data is always shifted out at one edge of the clock and sampled at the opposi...

Page 120: ...eries user must delay 4 system clock to set TDBR register after SS falling occur in SPI master to make sure SS sampling correct in slave Here is the example code in SPI master BC PA 12 Bit clear SS in...

Page 121: ...register before being transmitted Just prior to the beginning of a data transfer the data in TDBR is loaded into the Shift Data SFDR register NOTE When SPI module is enabled transmission does not sta...

Page 122: ...s 4 010 Fsys 8 011 Fsys 16 100 Fsys 32 101 Fsys 64 110 Fsys 128 111 Fsys 256 0 1 Add SPIHDEN control bit for programmable high current output in PortA 15 12 Using the library about programmable high c...

Page 123: ...equested if the SPI interrupt is enabled Refer to Section 2 10 3 4 Interrupt Flag Register 0 INTF0 for more details 3 8 5 SPI Transfer Format The SPI supports four different combinations of serial clo...

Page 124: ...ing Diagrams 3 8 6 1 SPI Master Mode Timing Diagram 6 5 4 3 2 1 LSB MSB MSB LSB 1 2 3 4 5 6 Data write to TBDR TXS SCK CPHA 1 CPOL 0 SCK CPHA 1 CPOL 1 SCK CPHA 0 CPOL 0 SCK CPHA 0 CPOL 1 MISO MOSI Sam...

Page 125: ...K CPHA 0 CPOL 1 MISO MOSI Sample Strobe TCF SS MSB LSB 1 2 3 4 5 6 SCK CYCLE 1 2 8 7 6 5 4 3 6 5 4 3 2 1 MSB LSB Figure 3 20a SPI Slave Mode Timing CPHA 0 Diagram Data write to TDBR TXS SCK CPHA 1 CPO...

Page 126: ...TCF Write Byte1 Write Byte2 Read ByteA Read ByteB Write Byte3 Write Byte4 Figure 3 21a Consecutively Receiving Bytes Timing Master or Slave Mode CPOL 0 CPHA 1 Diagram Byte 1 Byte 2 Datawriteto TDBR T...

Page 127: ...are to read Data is stored right aligned in RDBR When the receive data transfer is completed which means that the specified number of data bits has been shifted through SFDR the following events will...

Page 128: ...r exmple the system clock is 16MHz in SPI slave and SPI master The master SPR should be 010 011 100 101 110 111 NOTE Before transmission begin user must set dummy data into the TDBR or TDBR to prevent...

Page 129: ...er end Write data toTDBR TXS 1 Setting SPICR SPIEN 1 Last data complete TCF 0 End Start YES NO YES YES NO NO SPI empty data transfer mode Is TDBR full TXS 1 Transfer or receive complete TCF 0 Write da...

Page 130: ...0304 0X0506 Define test data for SPI transfer DW 0X0708 0X090A 0X0B0C DW 0X0D0E 0X0F10 R0 SPI_Temp_Data R1 TESTDATA R2 R0 0x0008 _COUNT R0 P R1 Read 8 word data form data ROM to data RAM SPI_Temp_Data...

Page 131: ...er applications e g sensor amplifier current amplifier analog filter etc AGC AGC MICIN 2 2K 470 68K 1n AVDD OP OP 1 2VREF 22uF 1 2VREF 10u AGCEN AMPO AMPEN Figure 3 23 Microphone Front End Block Diagr...

Page 132: ...AMPEN AGCEN Control Register Attributes and Definitions AMPEN AGCEN2 Gain Amplifiers AGC VOX Application Field 0 0 Disable Disable 0 1 Disable Enable 1 0 Enable Disable Sensor amplifier current ampli...

Page 133: ...age gain The Post Amplifier is a non inverting type operation amplifier 3 9 1 2 AGC Function Located within the Pre amplifier stage is the Automatic Gain Control AGC unit The AGC has an adjustable tim...

Page 134: ...7 Set DAC Un Sign mode always pass mode vol 3mA max AD_SINGLE 5 1 Set ADC Single mode ch5 clk1 FPLL 16 BC BUF_PD 0 _ADC_WAIT5 NOP NOP NOP Wait ADC interrupt BTEST BUF_PD 0 IF TC JMP _ADC_WAIT5 R0 BUF...

Page 135: ...3 24e eSL and eSLZ000 only PORTD 7 0 OUT See Figure 3 24f eSL and eSLZ000 only WEB RDB CEB TDO DROMA 23 0 OUT See Figure 3 24f eSLZ000 only DROMD 15 0 IN OUT See Figure 3 24g eSLZ000 only TDI TCK TMS...

Page 136: ...gger Input Pad with Pull Up Resistor Figure 3 24a Input Pad with Pull Up Resistor 3 10 1 2 CMOS Schmitt Trigger Input Pad with Pull Down Resistor Figure 3 24b Input Pad with Pull Down Resistor 3 10 1...

Page 137: ...rtB NOTE PORTB GPIO OE is active high when OE 1 I PAD PU is active high when PU 1 Resistor ON 3 10 1 5 CMOS Input Output Pads with Pull Up Resistor PortC Figure 3 24e Input Output Pads PortC NOTE OE i...

Page 138: ...CMOS Output Only Pads Figure 3 24f Output Only Pads 3 10 1 7 CMOS Input Output Only Pads Figure 3 24g Input Output Only Pads 3 10 1 8 Touch Panel Detection Pads Figure 3 24h Touch Panel Detection Pads...

Page 139: ...Peripheral Control 127 3 10 1 9 CMOS Schmitt Trigger Input Pads Figure 3 24i Trigger Input Pad 3 10 1 10 CMOS Input Only Pads Figure 3 24j Trigger Input Pad 3 10 1 11 CMOS Input Output Pads Figure 3 2...

Page 140: ...I DO HD PU WK Remarks PA 7 0 PA 8 Timer PA 9 Timer PA 10 EXINT PA 11 EXINT PA 14 12 PA 15 SPI PB 7 0 PB 15 8 Except eSLS PC 7 0 Except eSLS PD 7 0 GPIO Except eSLS Where DI Data Input PU Internal Pull...

Page 141: ...A Bit DIR Description Reset Value PORTA 15 0 R W Port A input and output data Register 0x0000 NOTE PortA 12 15 have programmable high current function Refer to Section 3 8 4 4 SPI Control Register SPI...

Page 142: ...R W 00 PCON1B 7 6 3 R W 00 PCON1B 9 8 4 R W 00 PCON1B 11 10 5 R W 00 PCON1B 13 12 6 R W 00 PCON1B 15 14 7 R W 00 C MOS input mode 01 C MOS output mode 10 C MOS input mode with pull up resistor 11 C MO...

Page 143: ...ved 00 PCONC 2 5 4 R W 00 C MOS input mode 01 C MOS output mode 10 C MOS input mode with pull up resistor 11 ADC2 input 00 PCONC 3 7 6 R W 00 C MOS input mode 01 C MOS output mode 10 C MOS input mode...

Page 144: ...e PCOND 0 0 R W 0 Without delay 1 Enable delay 0 3 11 3 Input Mode with Pull Up Resistor Delay Time The data rise time in input mode with pull up resistor is 1 1 s For example the input data is ready...

Page 145: ...s Manual Peripheral Control 133 Figure 3 25b I O Port Interfacing to BJT Figure 3 25c I O Port Driving a Relay eSL DACO a Bad design b Good design 5V Speaker Load eSL DACO 5V Speaker Load eSL PB 5 a B...

Page 146: ...T pins must be connected together to ground If the voltage is 5V the IOVDD_PWM IOVDD_PB IOVDD_PC are connected to 5V source voltage while VDD_CPU VDD_PM VDD_OSC VDD_ICE and AVDD_AD AVDD_DA must be con...

Page 147: ...0 1u 0 1u 0 1u 0 1u 10u 1 5u 0 1u 0 1u 0 1u 0 1u 5V IOVSS_PWM IOVSS_PB IOVSS_PC 3V Figure 3 26a eSL Regulator under 3V and 5V Supply Voltage AVDD_AD VDD_PM VDD_CPU AVDD_DA RVOUT RVIN IOVDD_PWM IOVDD_P...

Page 148: ......

Page 149: ...temperature and process variation Performance prediction is based on a combination of these three factors The central operating condition is characterized at 3 3V 25 C and typical process parameters...

Page 150: ...licable Pins Symbol Condition Rate Value Unit Power Supply Voltage VDD VDD TA 25 C 0 3 to 6 0 Input Voltage ALL INPUT VIN TA 25 C 0 3 to VDD 0 3 V Operating Temperature Range TA 40 to 85 Storage Tempe...

Page 151: ...s Symbol Condition Min Typ Max Unit 2 batteries 2 2 3 0 3 6 Power supply voltage VDD VDD 3 batteries 3 6 4 5 5 5 VIN1 VDD 0 7 VDD Input voltage VIN2 0 VDD 0 3 0 5 VDD 0 75 VDD Input threshold voltage...

Page 152: ...D 3V VOL 0 4V 7 10 PWM output high current PWM0 PWM1 IPWMH VDD 3V VOH VDD 2 Max volume 140 150 PWM output low current PWM0 PWM1 IPWML VDD 3V VOL VDD 2 Max volume 140 150 DAC output current DACO IDAC V...

Page 153: ...nt PWM0 PWM1 IPWMH VDD 3V VOH VDD 2 Max volume 140 150 PWM output low current PWM0 PWM1 IPWML VDD 3V VOL VDD 2 Max volume 140 150 DAC output current DACO IDAC VDD 2 2 3 3V 2 5 3 Regulator output high...

Page 154: ...Chapter 4 142 Electrical Characteristics eSL eSLS Series eSLZ000 User s Manual...

Page 155: ...6 PA 7 PA 8 PA 9 PA 10 PA 11 PA 12 PA 13 PA 14 PA 15 VCC_PB VSS_PM VDD_PM XP GND_PC YP XN AVSS_AD YN VREF PB 0 AVDD_AD PB 1 PB 2 PB 3 PB 4 PB 5 PB 6 PB 7 AMPO AGC MIC PB 8 PB 9 PB 10 PB 11 PB 12 PB 13...

Page 156: ...D TR2 D TR4 LS1 SPEAKER C1 10pF U1 eSLS 86 87 90 91 92 93 94 95 96 97 98 99 100 1 2 10 11 12 13 30 50 14 46 15 16 17 18 19 20 21 39 41 40 62 68 56 67 60 58 59 61 57 65 64 63 66 85 88 89 PA 0 PA 1 PA 2...

Page 157: ...DD_PM XP IOVSS_PC YP XN AVSS_AD YN AVDD_DA PB 0 AVDD_AD PB 1 PB 2 PB 3 PB 4 PB 5 PB 6 PB 7 AMPO AGC MIC PB 8 PB 9 PB 10 PB 11 PB 12 PB 13 PB 14 PB 15 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 IOVDD_PC V...

Page 158: ...se issue For example you can use on chip regulator to be the analog voltage source Or you can refer to development board reference circuit NOTE For different package type the system characteristic iss...

Page 159: ...0x07FFF SR Status register contains carry zero overflow flag status Stack 16 bits address software stacks for subroutine call and interrupt W C Word Cycle 6 1 2 Operand Symbol Description R0 R7 Genera...

Page 160: ...s These symbols which are written after a valid instruction are used to clarify such instructions only They do not operate as part of the instruction Symbol Description addr16 The value of 16 Bits RAM...

Page 161: ...1 Rd Rs Rs Rd 1 1 Rd Rs Rs Rd 1 1 Rd Rs Rs Rd 1 1 Rd RAM16 L addr16 Rd 2 2 RAM16 Rs L Rs addr16 2 2 Rd imm16 imm16 Rd 2 2 Rd imm16 imm16 Rd 2 2 Rd l imm8 imm8 Rd l 0 Rh 1 1 Rd h imm8 imm8 Rd h 1 1 Rd...

Page 162: ...2 ADC Rd Rs RAM16 C Rs addr16 C Rd 2 2 Rd Rs Rt Rs Rt Rd 1 1 Rd Rs Rt Rs Rt Rd 1 1 Rd Rs Rt Rs Rt Rd 1 1 Rd Rd imm6 Rd imm6 Rd 1 1 Rd Rs imm16 Rs imm16 Rd 2 2 Rd Rs imm16 Rs imm16 Rd 2 2 SUB Rd Rs RAM...

Page 163: ...s U Rt U D 1 1 D Rs Rt UU Rs U Rt U D 1 1 D Rs P Rt UU Rs U P Rt U D 1 2 1 1 D Rs P Rt UU Rs U P Rt U D 1 2 1 1 D Rs P Rt UU Rs U P Rt U D 1 2 1 1 MUL UU D Rs P Rt UU Rs U P Rt U D 1 2 1 1 DIV S D D R...

Page 164: ...Rs OR imm16 Rs imm16 Rd 2 2 Rd Rs OR imm16 Rs imm16 Rd 2 2 OR Rd Rs OR RAM16 Rs addr16 Rd 2 2 Rd Rs XOR Rt Rs Rt Rd 1 1 Rd Rs XOR Rt Rs Rt Rd 1 1 Rd Rs XOR Rt Rs Rt Rd 1 1 Rd Rd XOR imm6 Rd imm6 Rd 1...

Page 165: ...pdate SR register 1 2 1 1 1 Using RPT instruction to perform this operation only needs 1 cycle 6 2 4 Bit Operation Instructions Function Algebra Assembly Syntax Operation W C T N Z V C BS Rd b 1 Rd bi...

Page 166: ...P JMP Short_addr PC 1 Offset PC 1 1 2 2 IF CS JMP Long_addr If C 1 Long_add PC 2 2 JCS IF CS JMP Short_addr If C 1 PC 1 Offset PC 1 1 2 2 IF CC JMP Long_addr If C 0 Long_addr PC 2 2 JCC IF CC JMP Shor...

Page 167: ...1 1 2 2 IF GE JMP Long_addr If N V 0 Long_addr PC 2 2 JGE IF GE JMP Short_addr If N V 0 PC 1 Offset PC 1 1 2 2 IF HS JMP Long_addr If C 1 Long_addr PC 2 2 JHS IF HS JMP Short_addr If C 1 PC 1 Offset P...

Page 168: ...P Long_add If N V 1 Long_addr PC 2 2 JLT IF LT JMP Short_add If N V 1 PC 1 Offset PC 1 1 2 2 TRAP TRAP imm6 1 PC 1 TOS 2 SP 1 SP 3 imm6 vector number 2 PC 4 GIE 0 1 2 NOP NOP No operation 1 1 1 These...

Page 169: ...E2 TIE2 TIE1 TIE0 EXINTIE0 0x0D INTE1 0x0000 R W PDTIE ADIE SPLIMIE WDTIE 0x0E 0x0F Reserve 0x10 PC 0x0000 R W PC 15 0 0x11 SPA 0xuuuu R W SPA 15 0 0x12 RCR 0x0000 R W RCR 15 0 0x13 LCR 0x0000 R W LCR...

Page 170: ...RTC1 1 0 RTC0 1 0 0x40 SPICON 0x0000 R W SPIEN SPIHDEN CPHA CPOL SIZE MSTR SPR 2 0 0x41 TDBR 0x0000 R W TDBR 15 0 0x42 RDBR 0x0000 R RDBR 15 0 0x43 SPISR 0x0000 R TXS START TCF 0x44 0x4F Reserve 0x50...

Page 171: ...3 LCR 0x0000 R W LCR 15 0 0x14 LSA 0x0000 R W LSA 15 0 0x15 LEA 0x0000 R W LEA 15 0 0x16 INTP0 0x0000 R W DROMIP PWMPIP PWMDIP RTCIP 3 RTCIP2 RTCIP1 RTCIP0 EXINTIP1 TVIP 3 TIP3 TVIP2 TIP2 TIP1 TIP0 EX...

Page 172: ...R W PWMP 15 6 0x52 PWMCON 0x0000 R W PWMEN PWMDEN PWMVOL 1 0 PWMCLR PWM RPT 2 0 PWM MOD CENTR PWMOEN 1 0 PWMPS 1 0 0x53 DROMD 0x0000 R DROM DATA 15 0 0x54 DROMLA 0x0000 R W DROM LA 15 0 0x55 DROMHA 0x...

Page 173: ...5L6405 64M Bit NX25P10 1M Bit NX25P20 2M Bit Winbond NEX NX25P40 4M Bit NUMONXY M25P05 A 512K Bit NOTE The sector erase command in MXIC SPI flash MX25L512 is different form other vendors We recommand...

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