Elan eSL Series, User Manual

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Chapter 3
eSL/eSLS Series (+ eSLZ000) User’s Manual Peripheral Control
••••
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3
SPR: SPI clock rate selection
3-bits SPR is used to set the bit transfer rate for a master device.
Note that if the SPI is configured as a slave, the eSL slave SPI system frequency must be at
least, greater than eight times the master SPI serial clock frequency.
3.8.4.5 SPI Status Register (SPISR)
SPI Status Register Attributes and Definitions
:
SPISR Bit DIR. Description Reset Value
TXS
1
[2] R
TDBR status flag :
0: TDBR is empty
1: TDBR is full
0
TCF
2
[0] R
Transfer complete flag :
0: Transfer is completed
1:
Transfer is not completed
0
1
TXS: TDBR status flag
The transmit buffer becomes full (TXS=1) after it is written into. It becomes empty (TXS=0)
when data transfer begins and the transmitted value is loaded into the Shift register ( H/W set;
S/W cleared ).
2
TCF: transfer complete flag
The SPI hardware clears this bit to indicate that it has completed sending or receiving the last
bit of data and is ready for the next task. The received data is placed in the RDBR and this bit
is cleared at the same time
(
H/W set; H/W cleared
).
This flag causes an interrupt to be
requested if the SPI interrupt is enabled. Refer to Section 2.10.3.4, Interrupt Flag Register 0
(INTF0) for more details.
3.8.5 SPI Transfer Format
The SPI supports four different combinations of serial clock phase and polarity.
The user application code can select any of these combinations using the CPOL
and CPHA bits in the Control register.
The clock polarity and the clock phase should be identical for the master device
and the slave device involved in the communication link. The transfer format
from the master may be changed between transfers to adjust to various
requirements of a slave device.
For master, a transfer begins when data is written to TDBR and ends when TCF
is cleared. For slave with CPHA = 0, a transfer starts when /SS goes low and
ends when /SS returns high. In this case, SPIF is set at the middle of the last
SCK cycle when data is transferred from the shifter to the parallel data register,
but the transfer will keep on going until /SS goes high.
On the other hand, for slave with CPHA = 1, a transfer starts with the first active
edge of SCK and ends when TCF is cleared at the sampling edge of the last SCK
cycle.
When each transfer is completed, the TCF will be cleared and an interrupt will
be generated if the SPI interrupt is enabled. Refer to Section 2.10.3.4,
Interrupt
Flag Register 0 (INTF0) for more details.