Elan eSL Series, User Manual

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Chapter 3
eSL/eSLS Series (+ eSLZ000) User’s Manual Peripheral Control
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Chapter 3
Peripheral Control
3.1 Watchdog Timer (WDT)
The eSL Series chips are equipped with internal Basic/Watchdog Timer. This
timer is used to resume controller operation after being disturbed with noise,
system error, or other types of malfunctions. To configure WDT, the overflow
signal from 5-bit prescaler should be fed into the 8-bit Watchdog Timer clock
input as shown in the block diagram (Figure 3-1) under Section 3 .1.1. You can
enable or disable the Watchdog Timer through software by configuring the
WDTEN bit. If you do not want to use the WDT, the 5-bit Basic Timer can only
perform as a normal interval timer to request for interrupt service.
The Watchdog Timer Attributes and Resources:
Item Resource
Clock source F
32k
Usage register WDTCON
Interrupt sources WDTIF
Operation mode Overflow
The WDT clock source is from 32kHz oscillator. WDT time-out will cause a
CPU reset if WDTEN=1 and WDTREN=1. To prevent CPU reset from
occurring, the WDT value should be cleared by using “WDTC” bit before WDT
time-out. Setting the WDTEN bit will enable WDT to run. The initial state of
WDT is disabled.
A prescaler is also available to generate several clock rates as clock source for
WDT. The prescaler ratio is defined by WDTPSR1 & WDTPSR0.
NOTE
The use of higher WDT interrupt flag (WDTIF) during SLOW mode is NOT
recommended.
WDT function does NOT work during power save (GREEN/SLEEP) modes.