Elan eSL Series, User Manual

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Chapter 2
eSL/eSLS Series (+ eSLZ000) User’s Manual Architecture
••••
17
Chapter 2
Architecture
2.1 eSL System Block Diagram
As shown in the block diagram below, ELAN eSL Series (eSL/eSLS Series and
eSLZ000) utilize a modified Harvard architecture in such a way that the
memory is organized into two separated fields; Program ROM and Data RAM.
As the memory is separated, the central processing units can read/write data at
the same time. Furthermore, the I/O space has an independent address, i.e., the
I/O-mapped I/O. The different configurations of each domain are explained in
this chapter.
PWM
General
Purpose
Registers
Status Reg
17x17
Multiplier /
Divider
(+16 bit ALU)
Program
Counter
Instruction
Decoder
I/O Space
(SFR)
R
A
M
A
d
d
re
ss
in
g
R
eg
A
d
d
re
ss
in
g
Port A~D
ADC
DAC
INT
Contol
Signals
ACC D
IMM
#16
Timer
RTC
WDT
SPI
OSC/PLL
ROM
Control
Unit
ALU
RAM
I/
O
B
u
s
D
a
ta
B
u
s
I/
O
D
ir
ec
t
A
d
d
re
ss
in
g
Figure 2-1 ELAN eSL Series System Block Diagram.