Elan eSL Series, User Manual

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Chapter 2
56
••••
Architecture eSL/eSLS Series (+ eSLZ000) User’s Manual
2.10.3.6 Interrupt Priority Register 0 (INTP0)
INTP register determines the priority of interrupt sources in two priority levels:
1
st
priority
:
High, Low
2
nd
priority : Natural Order
When two or more registers are all set with equal High/Low priority, priority is
then determined by “Natural Order,” that is, in according with their bit value.
As indicated in the table below, Bit 0 has the highest priority and Bit 16 the
lowest.
INTPO Attributes and Definitions:
INTP0 Bit DIR. Description
Reset
Value
Remarks
EXINTIP0 [0] R/W 1: High; 0: Low 0
TIP0 [1] R/W 1: High; 0: Low 0
TIP1 [2] R/W 1: High; 0: Low 0
TIP2 [3] R/W
1:
High;
0:
Low 0
TOIP2 [4] R/W 1: High; 0: Low 0
TIP3 [5] R/W 1: High; 0: Low 0
TOIP3 [6] R/W 1: High; 0: Low 0
EXINTP1 [7] R/W 1: High; 0: Low 0
RTCIP0 [8] R/W
1:
High;
0:
Low 0
RTCIP1 [9] R/W 1: High; 0: Low 0
RTCIP2 [10] R/W 1: High; 0: Low 0
RTCIP3 [11] R/W 1: High; 0: Low 0
PWMDIP [12] R/W 1: High; 0: Low 0
PWMPIP [13] R/W 1: High; 0: Low 0
SPIP [14] R/W 1: High; 0: Low 0 Except eSLS
*
DROMIP [15] R/W 1: High; 0: Low 0
*
Do NOT use software to enable the interrupt in the eSLS ICs register. Otherwise, the whole
system will reset when interrupt occurs.
2.10.3.7 Interrupt Priority Register 1 (INTP1)
INTP1Attributes and Definitions:
INTP1 Bit DIR. Description
Reset
Value
Remarks
WDTIP [0] R/W 1: High; 0: Low 0
SPLIMIP [1] R/W 1: High; 0: Low 0
ADIP [2] R/W
1:
High;
0:
Low 0 Except eSLS
*
PDTIP [3] R/W 1: High; 0: Low 0 Except eSLS
*
*
Do NOT use software to enable the interrupt in the eSLS ICs register. Otherwise, the whole
system will reset when interrupt occurs.