EKF PC7-FESTIVAL, User Manual

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User Guide • PC7-FESTIVAL • CompactPCI® PlusIO CPU Board
3) IPMB SCL and SDA connected to CM238 PCH I
2
C port 1 via level shifter, pulled up with 1k to J1 pin A4
IPMB_PWR (+5V). IPMB_PWR can be sourced externally, and is also supplied by the PC7-FESTIVAL across a
Schottky diode.
4) All JTAG pins are NC since discouraged by CPCI specification Rev. 3.0
5) -12V connected to a decoupling capacitor only and not used on PC7-FESTIVAL
6) BD_SEL# connected to PLD input, however not in logical use by default
7) M66EN is detected by the PCI bridge in order to allow either 66MHz PCI backplane operation, or when pulled
low (by peripheral board) forces 33MHz clock.
Note: The PCI bridge can be setup also for 50MHz and 25MHz on customer request (resistor stuffing option).
When operating in 66MHz (50MHz) a V(I/O) voltage of +3.3V is mandatory.
8) +12V passed through to mezzanine connectors P-HSE and P-EXP, not required for PC7-FESTIVAL basic
operation
9) The 3.3V pins can be sourced by the PC7-FESTIVAL itself, for +5V only power supply designs (consider power
3.3V power requirements of peripheral boards).
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