User Guide • PC7-FESTIVAL • CompactPCI® PlusIO CPU Board
LAN Subsystem
The Ethernet LAN subsystem is composed of two Gigabit Ethernet ports: One Intel i219LM
Physical Layer Transceiver (PHY) using the PCH CM238 internal MAC and one Intel i210IT Gigabit
Ethernet Controller. These devices provide also legacy 10Base-T and 100Base-TX connectivity.
These Ethernet ports are fed to two RJ45 jacks located in the front panel. Each port includes the
following features:
<
One PCI Express lane per Ethernet port (250MB/s)
<
1000Base-Tx (Gigabit Ethernet), 100Base-TX (Fast Ethernet) and 10Base-T (Classic Ethernet)
capability.
<
Half- or full-duplex operation.
<
IEEE 802.3u, 802.3ab Auto-Negotiation for the fastest available connection.
<
Jumperless configuration (complete software-configurable).
Two bicoloured LEDs integrated into the dedicated RJ-45 connector in the front panel are used to
signal the LAN link, the LAN connection speed and activity status.
Each device is connected by a single PCI Express lane to the PCH. Their MAC addresses (unique
hardware number) are stored in dedicated FLASH/EEPROM components. The Intel Ethernet
software and drivers for the i219LM and i210IT are available from Intel's World Wide Web site for
download.
When managing the board by Intel Active Management Technology (iAMT), the dedicated
network port to do so is accessible by the RJ45 connector GbE1 (the upper port within the front
panel).
The i210 controller supports the IEEE 1588 Precision Time Protocol (the one connected to the
lower port within the front panel (GbE2)) and is capable to generate Pulse per Second (PPS) and
Pulse per Minute (PPM) signals that may be routed to the jumper J-GP and the
CompactPCI
®
PlusIO connector J2. These signals can be used to trigger events on Mezzanine Side Boards or
Peripheral Boards. The following routing is possible by UEFI/BIOS settings:
<
Pulse per Second (PPS):
J-GP Pin 1 and CompactPCI® SATA SCL J2 Pin D14
<
Pulse per Minute (PPM):
CompactPCI® SATA SDO J2 Pin D13
As an option, two 4-speed 2.5GBASE-T ports are available from the backplane, by means of the
P82-GBE low profile mezzanine module (from PCB Rev. 2022 off).
© EKF
- 35 -
ekf.com
Summary of Contents for PC7-FESTIVAL
Page 19: ...User Guide PC7 FESTIVAL CompactPCI PlusIO CPU Board Block Diagram EKF 19 ekf com...
Page 20: ...User Guide PC7 FESTIVAL CompactPCI PlusIO CPU Board Backplane Resources EKF 20 ekf com...
Page 21: ...User Guide PC7 FESTIVAL CompactPCI PlusIO CPU Board EKF 21 ekf com...
Page 22: ...User Guide PC7 FESTIVAL CompactPCI PlusIO CPU Board EKF 22 ekf com...
Page 26: ...User Guide PC7 FESTIVAL CompactPCI PlusIO CPU Board Top View Component Assembly EKF 26 ekf com...
Page 50: ...User Guide PC7 FESTIVAL CompactPCI PlusIO CPU Board 4HP Assembly w S48 SSD EKF 50 ekf com...
Page 52: ...User Guide PC7 FESTIVAL CompactPCI PlusIO CPU Board 4HP Assembly w C48 M2 EKF 52 ekf com...
Page 88: ...User Guide PC7 FESTIVAL CompactPCI PlusIO CPU Board EKF 88 ekf com...
Page 90: ...User Guide PC7 FESTIVAL CompactPCI PlusIO CPU Board EKF 90 ekf com...
Page 107: ...User Guide PC7 FESTIVAL CompactPCI PlusIO CPU Board Mechanical Details EKF 107 ekf com...