49
graphics display card does not support this feature.
AGP Master 1 WS Write (Disabled)
This implements a single delay when writing to the AGP Bus.
By default, two-wait states are used by the system, providing
greater stability.
AGP Master 1 WS Read (Disabled)
This implements a single delay when reading to the AGP Bus.
By default, two-wait states are used by the system, allowing
for greater stability.
Press <Esc> to return to the Advanced Chipset Features page.
CPU & PCI Bus Control
Scroll to this item and press <Enter> to view the following
screen:
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
CPU & PCI Bridge Control
Item Help
CPU to PCI Write Buffer
[Enabled]
PCI Master 0 WS Write
[Enabled]
PCI Delay Transaction
[Disabled]
Menu Level
↑
↓
→
←
: Move Enter : Select
+/-/PU/PD:Value:
F10: Save ESC: Exit F1:General Help
F5:Previous Values
F6:Fail-Safe Defaults
F7:Optimized Defaults
CPU to PCI Write Buffer (Enabled)
When enabled, writes from the CPU to PCU bus are buffered,
to compensate for the speed differences between the CPU
and PCI bus. When disabled, the writes are not buffered and
the CPU must wait until the write is complete before starting
another write cycle.
PCI Master 0 WS Write (Enabled)
When enabled, writes to the PCI bus are executed with zero
wait states.
PCI Delay Transaction (Disabled)
The mainboard’s chipset has an embedded 32-bit post write
buffer to support delay transactions cycles. Select Enabled to