Dynamic Engineering PCIe8LSwVPX3U User Manual Download Page 21

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standard temperature range 0

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PCIe8LSwVPX3U

1/2 PCIe card with VPX position
-ROHS [ROHS compliant parts and process]
-JTAG add JTAG header to rear of card
-AP add auxiliary power connector

http://www.dyneng.com/PCIe8LSwVPX3U.html

HDEterm68

http://www.dyneng.com/HDEterm68.html

68 pin SCSI II to 68 screw terminal converter with DIN
rail mounting.

HDEcabl68

http://www.dyneng.com/HDEcabl68.html

SCSI cables with latch blocks or thumbscrews and
various lengths are available. Custom lengths can be
ordered.

All information provided is Copyright Dynamic Engineering

Summary of Contents for PCIe8LSwVPX3U

Page 1: ...5060 831 457 8891 Fax 831 457 4793 http www dyneng com sales dyneng com Est 1988 User Manual PCIe8LSwVPX3U PCIe 8 Lane VPX 3U Compatible Carrier Corresponding Hardware Revision B Fab number 10 2014 11...

Page 2: ...s or changes in the product described in this document at any time and without notice Furthermore Dynamic Engineering assumes no liability arising out of the application or use of the device described...

Page 3: ...12 SCSI P2 VPX J2 USER VPX P2 12 VPX Module J1 PCIe lane assignments 13 VPX Module J0 Power assignments 14 APPLICATIONS GUIDE 15 Interfacing 15 Construction and Reliability 16 Thermal Considerations 1...

Page 4: ...RE 1 PCIE8LSWVPX3U CLOCKING 7 FIGURE 2 PCIE8LSWVPX3U P2 J2 USER P2 IO 12 FIGURE 3 PCIE8LSWVPX3U PCIE J1 13 FIGURE 4 PCIE8LSWVPX3U POWER J0 14 FIGURE 5 VITA SYSTEM CLOCKING MAXIMUM CONFIGURATION 17 FIG...

Page 5: ...stalled VPX card will need to match the settings for proper operation Extended testing has been performed in both modes using the VPX8LXMC3U adapter and an installed XMC Parallel TTL DMA operations we...

Page 6: ...ressing on VPX PCIe Switch Status LED s for FATAL Port Good0 and Port Good1 Optional EEPROM to configure PCIe Switch registers before boot With Rev B cards coax SMA are supplied on the SSC and NSSC po...

Page 7: ...h as Dynamic Engineering s VPX8LXMC3U x8 PCIe link REFCLKp n VPX PCIe Compliant Downstream Ports Clock with Spread Upstream Port Clock with Spread or No Spread X8 PCIe link SSC Off 25MHz Crystal PCIe...

Page 8: ...ctors tied to the NSSC 100 MHz These connectors can be used as a reference to the clock used by the Switch in NSSC mode J9 p J10 n are SMA connectors tied to the SSC 100 MHz These connectors can be us...

Page 9: ...00MHz NSSC on J7 and J8 7 O Disable 100MHz SSC on J10 and J11 6 C Selects 100MHz NSSC to be used by PCIe Switch s downstream port 5 O Selects PCIe REFCLK to be used by PCIe Switch s upstream port 4 C...

Page 10: ...led OFF Switch 5 PCIe Switch Upstream port clock select O Upstream port uses PCIe REFCLK from PCIe connector default setting C Upstream port uses 100MHz NSSC generated on board Switch 6 PCIe Switch Do...

Page 11: ...Port status The right hand LED is for the downstream port status The upstream port is connected to the PC and the downstream to your installed HW Steady on means Gen3 communications Flashing 2x per se...

Page 12: ...3 B13 9 43 G12 H12 E12 F12 10 44 C12 D12 B12 C12 11 45 E11 F11 D11 E11 12 46 A11 B11 A11 B11 13 47 G10 H10 E10 F10 14 48 C10 D10 B10 C10 15 49 E9 F9 D9 E9 16 50 A9 B9 A9 B9 17 51 G8 H8 E8 F8 18 52 C8...

Page 13: ...LN7 TX G8 H8 FIGURE 3 PCIE8LSWVPX3U PCIE J1 GND1 72 are connected to GND C1 D1 etc VPX0_DEF P1 SE7 4 are open I1 I3 I5 etc Please note 1 VPX definitions are relative to VPX PCIe connector definitions...

Page 14: ...C1 C2 D1 D2 5V A3 B3 C3 D3 F3 G3 H3 I3 3 3V AUX E5 M12 AUX OPEN P12AUX OPEN PERST C4 FIGURE 4 PCIE8LSWVPX3U POWER J0 Note 3 3V Aux is routed to PCIe 3 3V Aux and will be powered from PC power supply a...

Page 15: ...ed to match the set up and the wide base is stable The IC s will be on the outside toward the right when viewing the component side of the PCIe8LSwVPX3U This will allow for full access to your devices...

Page 16: ...e PCIe8LSwVPX3U is constructed out of 0 062 inch thick high temp RoHS compliant FR4 material The components on the PCIe8LSwVPX3U are tied into the internal power planes to spread the dissipated heat o...

Page 17: ...onfiguration of 32 circuits connected together PCIe8LSwVPX3U VITA System Clocking Maximum Configuration EIA 899 M LVDS 25MHz REFCLK with Modulation 100ppm max 50 duty cycle 5 PCI Express Host PCI Expr...

Page 18: ...ation and ATP test configuration VPX8LXMC3U LOOPBACK FIXTURE PCIe8LSwVPX3U XMC Parallel TTL PCI Express Host SCSI P2 VPX J2 FIGURE 6 PCIE8LSWVPX3U LOOPBACK TEST CONFIGURATION SCSI P2 Loopback connecti...

Page 19: ...ust accompany the return Dynamic Engineering will not be responsible for damages due to improper packaging of returned items For service on Dynamic Engineering Products not purchased directly from Dyn...

Page 20: ...ftware Interface Transparent design with no software required for adapter Installed VPX will determine control of that device Initialization switch selections for Global Addressing if needed Interface...

Page 21: ...card AP add auxiliary power connector http www dyneng com PCIe8LSwVPX3U html HDEterm68 http www dyneng com HDEterm68 html 68 pin SCSI II to 68 screw terminal converter with DIN rail mounting HDEcabl68...

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