Embedded Solutions
Page 9
DipSwitch Settings
SW1 (Switch 1): Global Address Settings
Position 1-5 corresponds to GA0-4. ‘0’ when closed (C). ‘1’ when open (O).
Position 6 corresponds to GAP. ‘0’ when closed (C). ‘1’ when open (O).
Position 7-8 are spare
SW2 (Switch 2): PCIe Switch and Clock Operation Settings
C = Closed, O = Open
Below are the standard settings that are used to configure the PCIeLSwVPX3U VPX
port for either NSSC or SSC operation. Details of each switch setting is also provided.
For NSSC (Non Spread Spectrum Independent Clocking) SW2 is set as follows:
8
O
-- Disable 100MHz NSSC on J7 and J8
7
O
-- Disable 100MHz SSC on J10 and J11
6
C
-- Selects 100MHz NSSC to be used by PCIe Switch’s downstream port
5
O
-- Selects PCIe REFCLK to be used by PCIe Switch’s upstream port
4
C
-- Disable 25MHz SSC clock output
3
O
-- I2C/SMBus not used for initial device configuration
2
C
-- Selects I2C protocol
1
O
-- Selects I2C protocol
For SSC (VITA spec Spread Spectrum Clocking) SW2 is set as follows:
8
O
-- Disable 100MHz NSSC on J7 and J8
7
O
-- Disable 100MHz SSC on J10 and J11
6
O
-- Selects 100MHz SSC to be used by PCIe Switch’s downstream port
5
O
-- Selects PCIe REFCLK to be used by PCIe Switch’s upstream port
4
O
-- Enable 25MHz SSC clock output
3
O
-- I2C/SMBus not used for initial device configuration
2
C
-- Selects I2C protocol
1
O
-- Selects I2C protocol
