Embedded Solutions
Page 18
Loopback Testing
For both the validation of, and the ATP for PCIE8LSwVPX3U, Dynamic Engineering
uses VPX8LXMC3U, XMC-PARALLEL-TTL, and a loopback fixture. Figure 6 shows the
validation and ATP test configuration.
VPX8LXMC3U
LOOPBACK
FIXTURE
PCIe8LSwVPX3U
XMC-Parallel-TTL
PCI Express
Host
SCSI
P2
VPX
J2
FIGURE 6
PCIE8LSWVPX3U LOOPBACK TEST CONFIGURATION
SCSI P2 Loopback connections are as follows:
32--->16
28--->12
24--->8
20--->4
31--->15
27--->11
23--->7
19--->3
66--->50
62--->46
58--->42
54--->38
65--->49
61--->45
57--->41
53--->37
30--->14
26--->10
22--->6
18--->2
29--->13
25--->9
21--->5
17--->1
64--->48
60--->44
56--->40
52--->36
63--->47
59--->43
55--->39
51--->35
