Embedded Solutions
Page 8
Headers and TestPoints
H2
is an optional JTAG header used to connect to VPX J0. The pin definitions are in
the silk. 1: 3.3V, 2: GND, 6: TMS, 4: TDO, 5: TDI, 3: TCK. Pin numbering matches
flying lead breakout on Xilinx programmer. Other vendor programmers can also be
used.
J1
is an optional use header to support the serial bus connection to the Switch. 1 =
SMDAT [pull-up 4.7K to 3.3V] 2 = gnd, 3 = SMCLK [pull-up 4.7K to 3.3V].
J2
&
J3
control the voltage on 33, 67 and 34, 68 of P2 respectively. 1-2 selects 3.3V
and 2-3 selects ground on those pins. The shunt and traces are rated for 1A. Not fuse
protected.
J4
&
J5
control the timing of the 3.3V and 5V power supplies. 1-2 selects delayed, 2-3
selects immediate, open selects off. J4 controls 3.3V and J5 controls 5V.
J7(p)
&
J8(n)
are SMA connectors tied to the NSSC 100 MHz. These connectors can
be used as a reference to the clock used by the Switch in NSSC mode.
J9(p)
&
J10(n)
are SMA connectors tied to the SSC 100 MHz. These connectors can
be used as a reference to the clock used by the Switch in SSC mode.
(J6 and J11 are unused reference designators)
J12
control the reference on the PCIe bezel. 1-2 selects AC coupled 2-3 selects DC
coupled and open is uncoupled to ground.
P3
is an optional power connector to allow for added 12V power to be used by the
PCIe8LSwVPX3U. The PCIe gold fingers allow for about 60W of power to be
consumed by the board across all VPX voltages including power supply losses. In
many cases the power budget is more than sufficient. If your VPX requires more power
please request the optional power connector [6 wire standard PC 2x3] to increase the
12V available. Both 12V entry points are diode coupled to prevent the current back-
feeding when an external or other supply is added.
P3
: 1, 2, 3= 12V, 4, 5, 6 = gnd.
