Dynamic Engineering PCIe8LSwVPX3U, User Manual

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Embedded Solutions Page 13
VPX Module J1 PCIe lane assignments
Signal J1
LN0-RX+ LN0-RX- A1 B1
LN0-TX+ LN0-TX- E1 F1
LN1-RX+ LN1-RX- C2 D2
LN1-TX+ LN1-TX- G2 H2
LN2-RX+ LN2-RX- A3 B3
LN2-TX+ LN2-TX- E3 F3
LN3-RX+ LN3-RX- C4 D4
LN3-TX+ LN3-TX- G4 H4
LN4-RX+ LN4-RX- A5 B5
LN4-TX+ LN4-TX- E5 F5
LN5-RX+ LN5-RX- C6 D6
LN5-TX+ LN5-TX- G6 H6
LN6-RX+ LN6-RX- A7 B7
LN6-TX+ LN6-TX- E7 F7
LN7-RX+ LN7-RX- C8 D8
LN7-TX+ LN7-TX- G8 H8
FIGURE 3 PCIE8LSWVPX3U PCIE/J1
GND1-72 are connected to GND. C1, D1 etc. VPX0_DEF&P1-SE7-4 are open I1, I3,
I5 etc.
Please note: (1) VPX definitions are relative to VPX. PCIe connector definitions are
relative to the PCIe bus. PCIe8LSwVPX3U reverses the lanes [TX/RX] between the
switch connections and the VPX J1 connector to compensate.
(2) VPX standard does not support the PCIe reference clock, but does support
independent clocking and SSC using a lower frequency REFCLK. It is expected the
VPX will provide a local reference clock. The PCIe Switch isolates Upstream from VPX
side.