Embedded Solutions
Page 5
Product Description
PCIe8LSwVPX3U is part of the Dynamic Engineering PCI and VPX Compatible family
of modular I/O components. PCIe8LSwVPX3U adapts a 3U VPX device to one PCIe
position.
PCIe8LSwVPX3U features a 16 lane switch buffering the connection between the Gold
fingers on the PCIe side and the VPX connector. The switch provides isolation to allow
the VPX side to operate at a different Gen level than the upstream port, and to provide
clock domain separation. In many cases it is desirable to have the upstream port run
Spread Spectrum enabled, and the VPX side operate with a fixed frequency clock. The
switch is Gen3 compliant and can operate with Gen 1, 2 or 3 on either port.
New with Revision B, PCIe8LSwVPX3U has support for both SSC and NSSC clocking
on the VPX port. REF_CLK is supported with a 25 MHz SSC. The switch can be
programmed via dipswitch to use SSC or NSSC on the downstream port. The installed
VPX card will need to match the settings for proper operation.
Extended testing has been performed in both modes using the VPX8LXMC3U adapter
and an installed XMC-Parallel-TTL. DMA operations were run overnight multiple times
in both modes without failure or TLP corrections required at the switch.
VPX devices have 3 connectors for Power, Bus IF, and IO respectively.
The power connector supplies 5V, 3.3V and 12V. PCIe has +12V available. Local
power supplies generate the 3.3V and 5V for the VPX module. Approximately 10A are
available on each rail. Voltage monitor circuits check under and overvoltage conditions
of each rail including the ones for the switch, and illuminate an LED when the voltage is
within tolerance.
The Bus IF connector provides up to 8 lanes from the downstream port on the switch.
Differential routing with length and impedance control are maintained for all relevant
PCIe signals on both sides of the switch.
The IO is routed from the VPX rear IO connector through to a SCSI connector mounted
at the bezel of PCIe8LSwVPX3U. Differential routing with impedance control and
matched length traces are employed.
