Embedded Solutions
Page 17
VITA Multipoint SSC Clocking implementation
The VITA Specification defines, and the PCIe8LSwVPX3U circuits support the VITA
maximum of 32 circuits connected together on a common transmission media.
The PCIe8LSwVPX3U implements this feature per VITA specification by generating,
supplying, and using a common 25MHz VITA SSC that is transmitted and received
using M-LVDS differential transceivers. The PCIe8LSwVPX3U can be optionally
configured to provide and use its VITA 25MHz SSC to supply the PCIe Switches’
downstream port with a 100MHz SSC clock generated from the received 25MHz VITA
SSC. Dynamic Engineering has validated the PCIe8LSwVPX3U VITA 25MHz SSC
clocking design using Dynamic Engineering VPX8LXMC3U carrier (also supports VITA
SSC clocking) and the XMC-PARALLEL-TTL board. Figure 5 shows the maximum
configuration of 32 circuits connected together.
PCIe8LSwVPX3U VITA System Clocking – Maximum Configuration
EIA-899 M-LVDS
25MHz /-
with Modulation
+/- 100ppm max
50% duty cycle +/- 5%
PCI Express
Host
PCI
Express
Switch
VPX Add-In Card29
VPX Add-In Card0
VPX Add-In Card1
VPX Add-In Card2
. .
PCIe link
REFCLKp/n
VPX/PCIe
Compliant
Downstream
Ports Clock
with Spread
Upstream
Port Clock with
Spread or
No Spread
PCIe link
PCIe link
PCIe link
PCIe link
SSC Off
25MHz
Crystal
PCIe compliant
100MHz Clock
No Spread
Straps
Clock
Generator
SSC Off
Straps
25MHz in
100MHz out
with SSC
Generator
1.8V
M-LVDS
Transmitter
25MHz
100MHz
25MHz in
25MHz SSC out
Clock Generator
M-LVDS
Receiver
Note: VPX Spec allows up to 32 circuits to be
connected to the common transmission media
Backplane differential /- lines are differentially terminated at each end with a resistor of 61.9 Ohms +/- 1%
PCIe
Compliant
Downstream
Ports Clock
No Spread
Downstream
Ports
Clock Select
PCIe compliant
100MHz Clock
with Spread
FIGURE 5
VITA SYSTEM CLOCKING – MAXIMUM CONFIGURATION
