DSP 104-plus, Reference Manual

Page: 53 / 140

158004.B00 43
4.4 PC/104 AND PC/104-Plus CLOCK AND RESET SIGNALS
4.4.1 PC/104 Clock and Reset Signals
Two PC/104 clocks are provided: the bus clock (BUSCLK) and an oscillator (OSC).
The BUSCLK runs at 8.33MHz. The OSC signal is a clock running at 14.3181MHz.
The TP400 can reset the PC/104 bus. See section 5 for details. The TP400 drives
the PC bus RESETDRV signal but cannot be reset by the RESETDRV signal.
The TP400 can be reset by issuing a low going pulse on the /RESET line of the J4
connector. In this way a system reset can be generated by an external signal or
switch. The TP400 will then force the RESETDRV signal of the PC/104 bus to be
driven. The TCDEVPLUS has a push button switch connected between /RESET and
GND. Pressing this switch momentarily will reset the system.
4.4.2 PC/104-Plus Clock and Reset Signals
The PC/104-Plus bus provides four 33.3MHz clocks, one for each of the possible
expansion boards.
The TP400 can reset the PC/104-Plus bus. See section 5 for details. The PC/104-
Plus bus provides an active low reset signal, PCIRST#, which is asserted whenever
the on-board hardware reset signal is asserted. The TP400 cannot be reset by
asserting the PCIRST# signal.
The TP400 can be reset by issuing a low going pulse on the /RESET line of the J4
connector. In this way a system reset can be generated by an external signal or
switch. The TP400 will then force the PCIRST# signal on the PCI bus to be driven.
PCIRST# can also be asserted by system software, and in fact this happens during
the BIOS POST. The TCDEVPLUS has a push button switch connected between
/RESET and GND. Pressing this switch momentarily will reset the system.