42
158004.B00
not 5V tolerant. This means that the TP400 cannot be used with PC/104-Plus or PCI
boards which have 5V signal levels. It will operate with 3.3V boards and with boards
which support either 3.3V or 5V operation. The TCVIDEO video capture board from
DSP Design can be used with the TP400. The TP400’s VI/O power supply pins are
configured to be at 3.3V.
Most of the PCI bus signals are bussed to all PCI boards in the system. Some signals
however are unique to each board. These are the IDSEL, clock, bus request and
grant pins. The interrupt pins also receive special treatment.
Each board receives a different address pin routed to its IDSEL pin. This allows each
PCI board to be allocated an individual "PCI Device" number. The IDSEL pin is used
during the configuration of each PCI Device. The PC/104-Plus spec states that the
four IDSEL signals should be connected to AD20-23.
There is a separate 33.3MHz clock for each board.
The bus request/bus grant signals are also routed to each board separately. Note
however that the TP400 only supports bus request/bus grant signals to the first two
PCI expansion boards.
The interrupt pins are "rotated" one position with every board. The means that if four
PCI boards are each asserting a single interrupt request (on their INTA# pin), the PCI
bridge (in the CS5530A chip) receives four different interrupt requests, one on each
of its four INTx# pins.
Table 8 describes the allocation of these point-to-point signals within a TP400
system. This table also notes the allocation of the IDSEL signals to the PCI functions
within the CS5530A chip. (The CS5530A incorporates two PCI functions - the USB
Controller and the "Chip set registers", which include the PCI to ISA bus bridge,
audio, video, IDE and power management functions).
PC/104+
MODULE
SLOT
SWITCH
POSIT-
ION
IDSEL
ADDR.
PCI
DEVICE
CLK PIN
REQ/
GNT
PAIR
5530A
INTA#
5530A
INTB#
5530A
INTC#
5530A
INTD#
1
0 or 4
AD20
Ah
CLK0
0
INTA#
INTB#
INTC#
INTD#
2
1 or 5
AD21
Bh
CLK1
1
INTB#
INTC#
INTD#
INTA#
3
2 or 6
AD22
Ch
CLK2
-
INTC#
INTD#
INTA#
INTB#
4
3 or 7
AD23
Dh
CLK3
-
INTD#
INTA#
INTB#
INTC#
5
- AD24
Eh - 1 INTA#
- - -
CS5530A Chip
Set Registers
- AD28
12h - - - - - -
CS5530A USB
Controller
- AD29
13h - - INTA#
- - -
TABLE 8 - PCI BUS RESOURCE ALLOCATIONS
The on-board Ethernet chip is normally configured as slot 4, although it could be
configured as a slot 5 device (see Appendix B for configuration options). The slot 5
entry in the above table is for the Ethernet chip when it is configured as slot 5.
For a full description of the PCI bus, see the PCI bus specification (www.pcisig.com).
The PC/104-Plus specification (version 1.1) is available on DSP Design's web site
(www.dspdesign.com).
Summary of Contents for 104-plus
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Page 136: ...J2 164004 C03 FIGURE J1 TP400ET MECHANICAL DRAWINGS FIGURE J2 TP400ET CIRCUIT DIAGRAM ...
Page 138: ...K2 158004 B00 FIGURE K1 TP300USB MECHANICAL DRAWINGS FIGURE K2 TP300USB CIRCUIT DIAGRAM ...