DSP 104-plus, Reference Manual

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3 PERIPHERALS
This section describes the I/O address map and the on-board peripherals.
3.1 I/O ADDRESS MAP
The TP400 features a number of on-board I/O mapped resources, and supports
access to the PC/104 bus I/O space as well.
All I/O mapped functions that are present on desktop PCs are present at the same
I/O addresses on the TP400. The TP400 is therefore compatible at the machine code
or register level with desktop PCs.
On-board I/O devices include registers within the Geode GX1 chip set, the Super I/O
chip, Ethernet chip and the extra UART chip. The Super I/O chip contains the floppy
disk controller, Utility Register, keyboard controller, calendar/clock module and the
serial and parallel I/O ports. The on-board I/O addresses are listed in Table 3.
I/O accesses are routed as follows. I/O accesses within the Geode GX1 processor
remain internal to this chip. I/O addresses that are within PCI bus devices (which
includes the registers internal to the CS5530A chip) are performed on the PCI bus.
Those I/O accesses that are not claimed by PCI bus peripherals are translated into
ISA bus accesses (by the CS5530A PCI bridge) and performed on the ISA bus.
Thus those addresses that are not on-board the TP400 are available for peripheral
devices on either the PC/104-Plus bus (PCI bus peripherals) or on the PC/104 bus
(ISA bus peripherals). The PCI bus peripherals get the first option to respond to an
access; only if there is no PCI response will the accesses be routed to the ISA bus
peripherals.
I/O addressing of PC/104 bus boards is reasonably straightforward: if an I/O address
is not used by on-board resources then it can be allocated to a PC/104 board. Putting
this another way, the addresses of PC/104 bus boards should be chosen to avoid the
on-board I/O resources.
Note that, in common with many ISA bus I/O boards, address decoding logic on
PC/104 boards often decodes only address lines A0 - A9, which can result in
“aliasing” - whereby a PC/104 board can respond to more than one address. For
example, a PC/104 bus board set for I/O address 200h may also respond at I/O
addresses 600h, A00h, E00h and so on.
I/O addressing of PC/104-Plus (PCI bus) peripherals is to a large extent
programmable, via each peripheral's PCI Configuration registers. These registers are
programmed by the BIOS following reset, in a process that should normally ensure
that no conflicts occur. PCI I/O addressing uses all 32 bits of the PCI address space,
so aliasing cannot occur.